From: Alexey Brodkin <redacted>
Date: Mon, 2 Jun 2014 18:53:55 +0400
On some platforms existing 100 msecond delay is not enough for DMA block to
recover after reset.
For example MAC DMA waits for all PHY input clocks are present and depending
on the board reset bit deassertion may take different amount of time.
Having this parameter easily configurable allows each board to have its own
value, while all exisiting boards will continue to use current default value of
100 msec.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Is there an upper bound for this you can just use?
It taking too long and timing out is an error condition, so just
using a limit value of "100" or something should be perfectly fine.
I don't think it's reasonable to put every conceivable nuance into
the DT nodes.
I'm not applying this patch, sorry.