From: Nicolas Ferre <hidden> Date: 2013-05-13 16:05:11
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
---
Documentation/devicetree/bindings/net/macb.txt | 2 ++
drivers/net/ethernet/cadence/macb.c | 15 +++++++++++++--
drivers/net/ethernet/cadence/macb.h | 5 +++++
3 files changed, 20 insertions(+), 2 deletions(-)
@@ -6,6 +6,8 @@ Required properties: Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem".+ Use "cdns,zynq-7000-gem" for devices based on Cadence GEM with alternative+ options enabled (ISR clear on write). - reg: Address and length of the register set for the device - interrupts: Should contain macb interrupt - phy-mode: String, operation mode of the PHY interface.
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
@@ -6,6 +6,8 @@ Required properties: Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem".+ Use "cdns,zynq-7000-gem" for devices based on Cadence GEM with alternative+ options enabled (ISR clear on write).- reg: Address and length of the register set for the device- interrupts: Should contain macb interrupt- phy-mode: String, operation mode of the PHY interface.
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <redacted>
Best Regards,
J.
Hi!
On Mon, May 13, 2013 at 06:05:05PM +0200, Nicolas Ferre wrote:
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
---
Documentation/devicetree/bindings/net/macb.txt | 2 ++
drivers/net/ethernet/cadence/macb.c | 15 +++++++++++++--
drivers/net/ethernet/cadence/macb.h | 5 +++++
3 files changed, 20 insertions(+), 2 deletions(-)
Looks okay to me:
Acked-by: Steffen Trumtrar <redacted>
Thanks,
Steffen
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On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
All right, that's a pity.
The only issue that remains then is the obligation to use CONFIG_OF,
or:
+#if defined(CONFIG_OF)
+ dev_id = of_match_device(macb_dt_ids, &pdev->dev);
+ if (dev_id)
+ bp->caps = (u32)dev_id->data;
+
+#endif
?
Hein
On May 14, 2013, at 3:18 PM, Hein Tibosch [off-list ref] wrote:
On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
All right, that's a pity.
The only issue that remains then is the obligation to use CONFIG_OF,
or:
+#if defined(CONFIG_OF)
+ dev_id = of_match_device(macb_dt_ids, &pdev->dev);
+ if (dev_id)
+ bp->caps = (u32)dev_id->data;
+
+#endif
?
no need as of_match_device is a inline of !OF
Best Regards,
J.
Hein
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From: Michal Simek <monstr@monstr.eu> Date: 2013-05-14 07:49:46
On 05/14/2013 09:31 AM, Hein Tibosch wrote:
On 5/14/2013 3:22 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 3:18 PM, Hein Tibosch [off-list ref] wrote:
quoted
On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
All right, that's a pity.
The only issue that remains then is the obligation to use CONFIG_OF,
or:
+#if defined(CONFIG_OF)
+ dev_id = of_match_device(macb_dt_ids, &pdev->dev);
+ if (dev_id)
+ bp->caps = (u32)dev_id->data;
+
+#endif
?
no need as of_match_device is a inline of !OF
Sorry, here's the complete compiler error:
drivers/net/ethernet/cadence/macb.c: In function 'macb_probe':
drivers/net/ethernet/cadence/macb.c:1601: error: 'macb_dt_ids' undeclared (first use in this function)
Earlier, 'macb_dt_ids' is only defined when using OF
The trick is in using of_match_ptr. It means remove that CONFIG_OF around macb_dt_ids too.
[linux-2.6.x]$ grep -rn "of_match_ptr" include/linux/
include/linux/of.h:314:#define of_match_ptr(_ptr) (_ptr)
include/linux/of.h:508:#define of_match_ptr(_ptr) NULL
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
On 5/14/2013 3:22 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On May 14, 2013, at 3:18 PM, Hein Tibosch [off-list ref] wrote:
quoted
On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
All right, that's a pity.
The only issue that remains then is the obligation to use CONFIG_OF,
or:
+#if defined(CONFIG_OF)
+ dev_id = of_match_device(macb_dt_ids, &pdev->dev);
+ if (dev_id)
+ bp->caps = (u32)dev_id->data;
+
+#endif
?
no need as of_match_device is a inline of !OF
Sorry, here's the complete compiler error:
drivers/net/ethernet/cadence/macb.c: In function 'macb_probe':
drivers/net/ethernet/cadence/macb.c:1601: error: 'macb_dt_ids' undeclared (first use in this function)
Earlier, 'macb_dt_ids' is only defined when using OF
Best regards,
Hein
On 5/14/2013 3:22 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 3:18 PM, Hein Tibosch [off-list ref] wrote:
quoted
On 5/14/2013 1:52 PM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
All right, that's a pity.
The only issue that remains then is the obligation to use CONFIG_OF,
or:
+#if defined(CONFIG_OF)
+ dev_id = of_match_device(macb_dt_ids, &pdev->dev);
+ if (dev_id)
+ bp->caps = (u32)dev_id->data;
+
+#endif
?
no need as of_match_device is a inline of !OF
Sorry, here's the complete compiler error:
drivers/net/ethernet/cadence/macb.c: In function 'macb_probe':
drivers/net/ethernet/cadence/macb.c:1601: error: 'macb_dt_ids' undeclared (first use in this function)
Earlier, 'macb_dt_ids' is only defined when using OF
The trick is in using of_match_ptr. It means remove that CONFIG_OF around macb_dt_ids too.
[linux-2.6.x]$ grep -rn "of_match_ptr" include/linux/
include/linux/of.h:314:#define of_match_ptr(_ptr) (_ptr)
include/linux/of.h:508:#define of_match_ptr(_ptr) NULL
yes of course, clever.
I tested the patch with that change on my avr32 platform and like to add:
Reported-by: Hein Tibosch <redacted>
Tested-by: Hein Tibosch <redacted>
Thanks,
Hein
From: Nicolas Ferre <hidden> Date: 2013-05-14 09:16:12
On 13/05/2013 18:05, Jean-Christophe PLAGNIOL-VILLARD :
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
As said by Hein, we cannot use the IP revision number. *But* we may have the opportunity to read this integration configuration in the Design Configuration Register 1 (DCFG1 already used for determining data bus width).
So, Michal or Steffen, can you please tell me the value of:
-> bit 23 at register address 0x280: mine is "1" which should mean "IRQ read clear", yours should be "0".
Hein, in case of use of the MACB, we do not have this register included, so I will avoid to run the test when using MACB (we already have this information).
If it works, I plan to rewrite the patch but taking this information instead of the device tree compatibility string.
Best regards,
@@ -6,6 +6,8 @@ Required properties: Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb". Use "cnds,pc302-gem" for Picochip picoXcell pc302 and later devices based on the Cadence GEM, or the generic form: "cdns,gem".+ Use "cdns,zynq-7000-gem" for devices based on Cadence GEM with alternative+ options enabled (ISR clear on write).- reg: Address and length of the register set for the device- interrupts: Should contain macb interrupt- phy-mode: String, operation mode of the PHY interface.
From: Michal Simek <monstr@monstr.eu> Date: 2013-05-14 11:38:55
On 05/14/2013 11:16 AM, Nicolas Ferre wrote:
On 13/05/2013 18:05, Jean-Christophe PLAGNIOL-VILLARD :
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
As said by Hein, we cannot use the IP revision number. *But* we may have the opportunity to read this integration configuration in the Design Configuration Register 1 (DCFG1 already used for determining data bus width).
So, Michal or Steffen, can you please tell me the value of:
-> bit 23 at register address 0x280: mine is "1" which should mean "IRQ read clear", yours should be "0".
Hein, in case of use of the MACB, we do not have this register included, so I will avoid to run the test when using MACB (we already have this information).
If it works, I plan to rewrite the patch but taking this information instead of the device tree compatibility string.
yep. Will be good to detect it instead of new compatible string.
Also is there an option to remove "CONFIG_ARCH_AT91"?
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
From: Nicolas Ferre <hidden> Date: 2013-05-14 12:30:59
On 14/05/2013 13:38, Michal Simek :
On 05/14/2013 11:16 AM, Nicolas Ferre wrote:
quoted
On 13/05/2013 18:05, Jean-Christophe PLAGNIOL-VILLARD :
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
As said by Hein, we cannot use the IP revision number. *But* we may have the opportunity to read this integration configuration in the Design Configuration Register 1 (DCFG1 already used for determining data bus width).
So, Michal or Steffen, can you please tell me the value of:
-> bit 23 at register address 0x280: mine is "1" which should mean "IRQ read clear", yours should be "0".
here is the whole reg map for zynq.
Reg 0x280 is undocumented in our TRM.
Please decode it not sure if bit 0 is LSB or MSB.
Bit 0 is LSB.
Value of DCFG1 is 0x02500111 so I read '0' for this value which should be good.
I write a new patch immediately.
Hein, in case of use of the MACB, we do not have this register included, so I will avoid to run the test when using MACB (we already have this information).
If it works, I plan to rewrite the patch but taking this information instead of the device tree compatibility string.
yep. Will be good to detect it instead of new compatible string.
Also is there an option to remove "CONFIG_ARCH_AT91"?
Okay, I have a look at this as-well.
Best regards,
--
Nicolas Ferre
From: Nicolas Ferre <hidden> Date: 2013-05-14 13:00:29
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
---
v2: - use DCFG1 bit 23 integration information instead of device tree
compatibility string to retreive information about c-o-r vs. c-o-w ISR.
- move configuration in macb_init_hw() function instead of probe() - at
"open" time.
As I have changed the most of this patch, I will collect your Ack and feedback
just like a new patch. Thanks for your help...
Bye,
drivers/net/ethernet/cadence/macb.c | 18 ++++++++++++++++--
drivers/net/ethernet/cadence/macb.h | 7 +++++++
2 files changed, 23 insertions(+), 2 deletions(-)
Hi Nicolas,
On 5/14/2013 9:00 PM, Nicolas Ferre wrote:
quoted hunk
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
---
v2: - use DCFG1 bit 23 integration information instead of device tree
compatibility string to retreive information about c-o-r vs. c-o-w ISR.
- move configuration in macb_init_hw() function instead of probe() - at
"open" time.
As I have changed the most of this patch, I will collect your Ack and feedback
just like a new patch. Thanks for your help...
Bye,
drivers/net/ethernet/cadence/macb.c | 18 ++++++++++++++++--
drivers/net/ethernet/cadence/macb.h | 7 +++++++
2 files changed, 23 insertions(+), 2 deletions(-)
Just re-tested with the above patch and it works like before,
also iperf results are unaffected (57/100 Mbit).
Tested-by: Hein Tibosch <redacted>
Thanks a lot,
Hein
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
---
v2: - use DCFG1 bit 23 integration information instead of device tree
compatibility string to retreive information about c-o-r vs. c-o-w ISR.
- move configuration in macb_init_hw() function instead of probe() - at
"open" time.
As I have changed the most of this patch, I will collect your Ack and feedback
just like a new patch. Thanks for your help...
Bye,
drivers/net/ethernet/cadence/macb.c | 18 ++++++++++++++++--
drivers/net/ethernet/cadence/macb.h | 7 +++++++
2 files changed, 23 insertions(+), 2 deletions(-)
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using the Design Configuration Register 1 information and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
From: Michal Simek <monstr@monstr.eu> Date: 2013-06-04 06:16:00
On 05/14/2013 07:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <redacted>
Was this added to any queue or branch?
I would like to enable macb for zynq and not sure if "cdns,zynq-7000-gem"
compatible string goes to mainline.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
On Tue, Jun 04, 2013 at 08:15:45AM +0200, Michal Simek wrote:
On 05/14/2013 07:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <redacted>
Was this added to any queue or branch?
I would like to enable macb for zynq and not sure if "cdns,zynq-7000-gem"
compatible string goes to mainline.
Hi!
This is already in next, but you can use the default compatible as the
DCR1 is used instead of DT binding.
Regards,
Steffen
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From: Michal Simek <monstr@monstr.eu> Date: 2013-06-04 06:55:05
On 06/04/2013 08:49 AM, Steffen Trumtrar wrote:
On Tue, Jun 04, 2013 at 08:15:45AM +0200, Michal Simek wrote:
quoted
On 05/14/2013 07:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <redacted>
Was this added to any queue or branch?
I would like to enable macb for zynq and not sure if "cdns,zynq-7000-gem"
compatible string goes to mainline.
Hi!
This is already in next, but you can use the default compatible as the
DCR1 is used instead of DT binding.
Ah ok. It was added there without cdns,zynq-7000-gem compatible string.
BTW: I have asked Soren to update your patch on the top of his clock changes.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
From: Nicolas Ferre <hidden> Date: 2013-06-04 07:51:55
On 04/06/2013 08:49, Steffen Trumtrar :
On Tue, Jun 04, 2013 at 08:15:45AM +0200, Michal Simek wrote:
quoted
On 05/14/2013 07:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <redacted>
Was this added to any queue or branch?
I would like to enable macb for zynq and not sure if "cdns,zynq-7000-gem"
compatible string goes to mainline.
Hi!
This is already in next, but you can use the default compatible as the
From: Michal Simek <monstr@monstr.eu> Date: 2013-06-04 07:57:33
On 06/04/2013 09:51 AM, Nicolas Ferre wrote:
On 04/06/2013 08:49, Steffen Trumtrar :
quoted
On Tue, Jun 04, 2013 at 08:15:45AM +0200, Michal Simek wrote:
quoted
On 05/14/2013 07:52 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On 08:58 Tue 14 May , Hein Tibosch wrote:
quoted
On 5/14/2013 12:05 AM, Jean-Christophe PLAGNIOL-VILLARD wrote:
quoted
On May 14, 2013, at 12:05 AM, Nicolas Ferre [off-list ref] wrote:
quoted
Commit 749a2b6 (net/macb: clear tx/rx completion flags in ISR)
introduces clear-on-write on ISR register. This behavior is not always
implemented when using Cadence MACB/GEM and is breaking other platforms.
We are using a new Device Tree compatibility string and a capability
property to actually activate this clear-on-write behavior on ISR.
Reported-by: Hein Tibosch <redacted>
Signed-off-by: Nicolas Ferre <redacted>
can we detect it via the IP?
This was my first proposal, have it based on the value of MACB's
register 'MID' (offset 0x00fc, lower 16 bits).
On avr32 it reads: 0x0000010D, on Zynq it reports 0x00000119
So for the moment, CAPS_ISR_CLEAR_ON_WRITE could be set if the revision
equals to 0x00000119?
so no it will not work
as the gem on sama5 is 00020119
so version 0x119 too
nico
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <redacted>
Was this added to any queue or branch?
I would like to enable macb for zynq and not sure if "cdns,zynq-7000-gem"
compatible string goes to mainline.
Hi!
This is already in next, but you can use the default compatible as the
Even more: already in Linus' tree!
Ah I see. v2 is in thunderbird in the same thread and I didn't check this
version for compatible string.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
Maintainer of Linux kernel - Xilinx Zynq ARM architecture
Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform