Re: [PATCH] can: flexcan: fix irq flooding by clearing all interrupt sources
From: Marc Kleine-Budde <mkl@pengutronix.de>
Date: 2011-12-12 15:31:16
Also in:
linux-can
On 12/12/2011 04:09 PM, Wolfgang Grandegger wrote:
As pointed out by Reuben Dowle and Lothar Waßmann, the TWRN_INT, RWRN_INT, BOFF_INT interrupt sources need to be cleared as well to avoid interrupt flooding, at least for the Flexcan on i.MX28 SOCs. Furthermore, the interrupts are only cleared, if really one of those interrupt sources are pending (which is not the case for rx and tx done). CC: Reuben Dowle <redacted> CC: Lothar Waßmann <redacted> Signed-off-by: Wolfgang Grandegger <redacted>
Have you tested on mx25/mx35, does it have any negative side effects? My schedule is full until Friday, sorry cannot test here. Marc
quoted hunk ↗ jump to hunk
--- drivers/net/can/flexcan.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index 165a4c7..111f154 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c@@ -118,6 +118,9 @@ (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | FLEXCAN_ESR_BOFF_INT) #define FLEXCAN_ESR_ERR_ALL \ (FLEXCAN_ESR_ERR_BUS | FLEXCAN_ESR_ERR_STATE) +#define FLEXCAN_ESR_ALL_INT \ + (FLEXCAN_ESR_TWRN_INT | FLEXCAN_ESR_RWRN_INT | \ + FLEXCAN_ESR_BOFF_INT | FLEXCAN_ESR_ERR_INT) /* FLEXCAN interrupt flag register (IFLAG) bits */ #define FLEXCAN_TX_BUF_ID 8@@ -577,7 +580,9 @@ static irqreturn_t flexcan_irq(int irq, void *dev_id) reg_iflag1 = flexcan_read(®s->iflag1); reg_esr = flexcan_read(®s->esr); - flexcan_write(FLEXCAN_ESR_ERR_INT, ®s->esr); /* ACK err IRQ */ + /* ACK all bus error and state change IRQ sources */ + if (reg_esr & FLEXCAN_ESR_ALL_INT) + flexcan_write(reg_esr & FLEXCAN_ESR_ALL_INT, ®s->esr); /* * schedule NAPI in case of:
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