Re: [PATCH v11 3/6] flexcan: Fix up fsl-flexcan device tree binding.
From: Grant Likely <hidden>
Date: 2011-08-11 16:53:43
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linux-devicetree, linuxppc-dev
Possibly related (same subject, not in this thread)
- 2011-08-12 · Re: [PATCH v11 3/6] flexcan: Fix up fsl-flexcan device tree binding. · Robin Holt <hidden>
On Thu, Aug 11, 2011 at 10:07 AM, Robin Holt [off-list ref] wrote:
quoted hunk ↗ jump to hunk
This patch cleans up the documentation of the device-tree binding for the Flexcan devices on Freescale's PowerPC and ARM cores. Extra properties are not used by the driver so we are removing them. Signed-off-by: Robin Holt <redacted> To: Marc Kleine-Budde <mkl@pengutronix.de>, To: Wolfgang Grandegger <redacted>, To: U Bhaskar-B22300 <redacted> To: Scott Wood <redacted> To: Grant Likely <redacted> To: Kumar Gala <redacted> Cc: socketcan-core@lists.berlios.de, Cc: netdev@vger.kernel.org, Cc: PPC list <redacted> Cc: devicetree-discuss@lists.ozlabs.org --- .../devicetree/bindings/net/can/fsl-flexcan.txt | 69 ++++--------------- arch/powerpc/boot/dts/p1010rdb.dts | 10 +-- arch/powerpc/boot/dts/p1010si.dtsi | 10 +-- 3 files changed, 21 insertions(+), 68 deletions(-)diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 1a729f0..c78dcbb 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt@@ -1,61 +1,22 @@ -CAN Device Tree Bindings ------------------------- -2011 Freescale Semiconductor, Inc. +Flexcan CAN contoller on Freescale's ARM and PowerPC processors -fsl,flexcan-v1.0 nodes ------------------------ -In addition to the required compatible-, reg- and interrupt-properties, you can -also specify which clock source shall be used for the controller. +Required properties: -CPI Clock- Can Protocol Interface Clock - This CLK_SRC bit of CTRL(control register) selects the clock source to - the CAN Protocol Interface(CPI) to be either the peripheral clock - (driven by the PLL) or the crystal oscillator clock. The selected clock - is the one fed to the prescaler to generate the Serial Clock (Sclock). - The PRESDIV field of CTRL(control register) controls a prescaler that - generates the Serial Clock (Sclock), whose period defines the - time quantum used to compose the CAN waveform. +- compatible : Should be "fsl,<processor>-flexcan" and "fsl,flexcan"
Don't do this. "fsl,flexcan" is far too generic. Be specific to the soc part number or the ip core implementation version.
-Can Engine Clock Source
- There are two sources for CAN clock
- - Platform Clock It represents the bus clock
- - Oscillator Clock
+ An implementation should also claim any of the following compatibles
+ that it is fully backwards compatible with:
- Peripheral Clock (PLL)
- --------------
- |
- --------- -------------
- | |CPI Clock | Prescaler | Sclock
- | |---------------->| (1.. 256) |------------>
- --------- -------------
- | |
- -------------- ---------------------CLK_SRC
- Oscillator Clock
+ - fsl,p1010-flexcan
-- fsl,flexcan-clock-source : CAN Engine Clock Source.This property selects
- the peripheral clock. PLL clock is fed to the
- prescaler to generate the Serial Clock (Sclock).
- Valid values are "oscillator" and "platform"
- "oscillator": CAN engine clock source is oscillator clock.
- "platform" The CAN engine clock source is the bus clock
- (platform clock).
+- reg : Offset and length of the register set for this device
+- interrupts : Interrupt tuple for this device
-- fsl,flexcan-clock-divider : for the reference and system clock, an additional
- clock divider can be specified.
-- clock-frequency: frequency required to calculate the bitrate for FlexCAN.
+Example:
-Note:
- - v1.0 of flexcan-v1.0 represent the IP block version for P1010 SOC.
- - P1010 does not have oscillator as the Clock Source.So the default
- Clock Source is platform clock.
-Examples:
-
- can0@1c000 {
- compatible = "fsl,flexcan-v1.0";
- reg = <0x1c000 0x1000>;
- interrupts = <48 0x2>;
- interrupt-parent = <&mpic>;
- fsl,flexcan-clock-source = "platform";
- fsl,flexcan-clock-divider = <2>;
- clock-frequency = <fixed by u-boot>;
- };
+ can@1c000 {
+ compatible = "fsl,p1010-flexcan", "fsl,flexcan";
+ reg = <0x1c000 0x1000>;
+ interrupts = <48 0x2>;
+ interrupt-parent = <&mpic>;
+ };The diffstat for this patch looks too big because the whitespace has changed. Try to restrict whitespace changes so that the patch is friendly to reviewers. g.