[PATCH 2/2] DM9000B: Fix PHY power for network down/up

Subsystems: networking drivers, the rest

STALE5646d

8 messages, 3 authors, 2011-02-23 · open the first message on its own page

[PATCH 2/2] DM9000B: Fix PHY power for network down/up

From: Henry Nestler <hidden>
Date: 2011-02-20 21:45:01

DM9000 revision B needs 1 ms delay after PHY power on (see spec), and PHY
power must on in register DM9000_GPR before all other settings will change.
Remember, that register DM9000_GPR was not changed by reset sequence.

Without these fix the FIFO goes out of sync and sends wrong data after
sequence of "ifconfig ethX down ; sleep 3 ; ifconfig ethX up".
---
Kernel version 2.6.38-rc5

 drivers/net/dm9000.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2d4c4fc..5925569 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c

@@ -802,10 +802,7 @@ dm9000_init_dm9000(struct net_device *dev)
 	/* Checksum mode */
 	dm9000_set_rx_csum_unlocked(dev, db->rx_csum);
 
-	/* GPIO0 on pre-activate PHY */
-	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
 	iow(db, DM9000_GPCR, GPCR_GEP_CNTL);	/* Let GPIO0 output */
-	iow(db, DM9000_GPR, 0);	/* Enable PHY */
 
 	ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;

@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
 	if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
 		return -EAGAIN;
 
+	/* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
+	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
+	udelay(1000); /* delay needs by DM9000B */
+
 	/* Initialize DM9000 board */
 	dm9000_reset(db);
 	dm9000_init_dm9000(dev);

[PATCH 2/2] DM9000B: Fix PHY power for network down/up

From: Sergei Shtylyov <hidden>
Date: 2011-02-21 11:14:39

Hello.

On 21-02-2011 0:45, Henry Nestler wrote:

DM9000 revision B needs 1 ms delay after PHY power on (see spec), and PHY
power must on in register

    Couldn't parse that.

DM9000_GPR before all other settings will change.
Remember, that register DM9000_GPR was not changed by reset sequence.

Without these fix the FIFO goes out of sync and sends wrong data after

    s/these/this/

sequence of "ifconfig ethX down ; sleep 3 ; ifconfig ethX up".

[...]

quoted hunk

diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2d4c4fc..5925569 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c

[...]

quoted hunk

@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
  	if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
  		return -EAGAIN;

+	/* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
+	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
+	udelay(1000); /* delay needs by DM9000B */

    Why not mdelay(1)?

WBR, Sergei

[PATCH 2/2] DM9000B: Fix PHY power for network down/up

From: Henry Nestler <hidden>
Date: 2011-02-21 21:03:31

On 21.02.2011 12:14, Sergei Shtylyov wrote:

On 21-02-2011 0:45, Henry Nestler wrote:

quoted

DM9000 revision B needs 1 ms delay after PHY power on (see spec), and PHY
power must on in register

    Couldn't parse that.

This can read in manual DM900B-12-DS-F02 from September 2 2010, Page 14:
"If this Register 1FH bit 0 is updated from '1' to '0', the all
Registers can not be accessed within 1ms."

The example driver code waits 2 ms.

quoted

diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2d4c4fc..5925569 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c

[...]

quoted

@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
  	if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
  		return -EAGAIN;

+	/* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
+	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
+	udelay(1000); /* delay needs by DM9000B */

    Why not mdelay(1)?

Because udelay is the base of mdelay.
See include/linux/delay.h:31

#define mdelay(n) ... udelay((n)*1000)

-- 
Henry N.

[PATCH 2/2] DM9000B: Fix PHY power for network down/up

From: Sergei Shtylyov <hidden>
Date: 2011-02-22 12:36:02

Hello.

On 22-02-2011 0:03, Henry Nestler wrote:

quoted

DM9000 revision B needs 1 ms delay after PHY power on (see spec), and PHY
power must on in register

quoted

     Couldn't parse that.

    You seem to have missed a word in your patch description.

This can read in manual DM900B-12-DS-F02 from September 2 2010, Page 14:
"If this Register 1FH bit 0 is updated from '1' to '0', the all
Registers can not be accessed within 1ms."

    That I've understood.

The example driver code waits 2 ms.

quoted

diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2d4c4fc..5925569 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c

[...]

quoted

@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
   	if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
   		return -EAGAIN;

+	/* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
+	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
+	udelay(1000); /* delay needs by DM9000B */

quoted

     Why not mdelay(1)?

Because udelay is the base of mdelay.
See include/linux/delay.h:31

#define mdelay(n) ... udelay((n)*1000)

    And?

WBR, Sergei

[PATCH 2/2] DM9000B: Fix PHY power for network down/up

From: davem@davemloft.net (David Miller)
Date: 2011-02-22 18:24:10

From: Henry Nestler <redacted>
Date: Mon, 21 Feb 2011 22:03:31 +0100

On 21.02.2011 12:14, Sergei Shtylyov wrote:

quoted

On 21-02-2011 0:45, Henry Nestler wrote:

quoted

DM9000 revision B needs 1 ms delay after PHY power on (see spec), and PHY
power must on in register

    Couldn't parse that.

This can read in manual DM900B-12-DS-F02 from September 2 2010, Page 14:
"If this Register 1FH bit 0 is updated from '1' to '0', the all
Registers can not be accessed within 1ms."

The example driver code waits 2 ms.

quoted

diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2d4c4fc..5925569 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c

[...]

quoted

@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
  	if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
  		return -EAGAIN;

+	/* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
+	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
+	udelay(1000); /* delay needs by DM9000B */

    Why not mdelay(1)?

Because udelay is the base of mdelay.
See include/linux/delay.h:31

#define mdelay(n) ... udelay((n)*1000)

He is telling you to use mdelay(1) because it's clearer.  Please do
so.

[PATCH 2/2] DM9000B: Fix PHY power for network down/up

From: Henry Nestler <hidden>
Date: 2011-02-22 19:58:20

Hello David,

On 22.02.2011 19:24, David Miller wrote:

From: Henry Nestler <redacted>
Date: Mon, 21 Feb 2011 22:03:31 +0100

quoted

On 21.02.2011 12:14, Sergei Shtylyov wrote:

quoted

On 21-02-2011 0:45, Henry Nestler wrote:

quoted

+	udelay(1000); /* delay needs by DM9000B */

    Why not mdelay(1)?

Because udelay is the base of mdelay.
See include/linux/delay.h:31

#define mdelay(n) ... udelay((n)*1000)

He is telling you to use mdelay(1) because it's clearer.  Please do
so.

Thanks, that text explains it better. No problem. I will resend this patch.

-- 
Henry N.

[PATCHv2 2/2] DM9000B: Fix PHY power for network down/up

From: Henry Nestler <hidden>
Date: 2011-02-22 21:29:42

DM9000 revision B needs 1 ms delay after PHY power-on.
PHY must be powered on by writing 0 into register DM9000_GPR before
all other settings will change (see Davicom spec and example code).

Remember, that register DM9000_GPR was not changed by reset sequence.

Without this fix the FIFO is out of sync and sends wrong data after
sequence of "ifconfig ethX down ; ifconfig ethX up".
---
Kernel version 2.6.38-rc5

 drivers/net/dm9000.c |    7 ++++---
 1 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/dm9000.c b/drivers/net/dm9000.c
index 2d4c4fc..5925569 100644
--- a/drivers/net/dm9000.c
+++ b/drivers/net/dm9000.c

@@ -802,10 +802,7 @@ dm9000_init_dm9000(struct net_device *dev)
 	/* Checksum mode */
 	dm9000_set_rx_csum_unlocked(dev, db->rx_csum);

-	/* GPIO0 on pre-activate PHY */
-	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
 	iow(db, DM9000_GPCR, GPCR_GEP_CNTL);	/* Let GPIO0 output */
-	iow(db, DM9000_GPR, 0);	/* Enable PHY */

 	ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;

@@ -1194,6 +1191,10 @@ dm9000_open(struct net_device *dev)
 	if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev))
 		return -EAGAIN;

+	/* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */
+	iow(db, DM9000_GPR, 0);	/* REG_1F bit0 activate phyxcer */
+	mdelay(1); /* delay needs by DM9000B */
+
 	/* Initialize DM9000 board */
 	dm9000_reset(db);
 	dm9000_init_dm9000(dev);

[PATCHv2 2/2] DM9000B: Fix PHY power for network down/up

From: davem@davemloft.net (David Miller)
Date: 2011-02-23 22:30:13

From: Henry Nestler <redacted>
Date: Tue, 22 Feb 2011 22:29:42 +0100

DM9000 revision B needs 1 ms delay after PHY power-on.
PHY must be powered on by writing 0 into register DM9000_GPR before
all other settings will change (see Davicom spec and example code).

Remember, that register DM9000_GPR was not changed by reset sequence.

Without this fix the FIFO is out of sync and sends wrong data after
sequence of "ifconfig ethX down ; ifconfig ethX up".

I've applied both of your patches, thanks.

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