Re: [PATCH] Fix SJA1000 command register writes on SMP systems

On 17.05.2010 16:29, Wolfgang Grandegger wrote:

Hi Oliver,

On 05/17/2010 01:06 PM, Oliver Hartkopp wrote:

quoted

The SJA1000 command register is concurrently written in the rx-path to free
the receive buffer _and_ in the tx-path to start the transmission.
On SMP systems this leads to a write stall in the tx-path, which can be
solved by adding some locking for the command register in the SMP case.

We should explain why a write stall can happen. Here is the relavant
part from the SJA1000 data sheet, 6.4.4 COMMAND REGISTER (CMR):

"Between two commands at least one internal clock cycle is needed in
order to proceed. The internal clock is half of the external oscillator
frequency."

The delay directly after the register access can only be guaranteed when there
is some locking around the command register write access.

In the end it boils down to a SMP issue again as this is (from all known
environments) the only case, where the problem appears in reality.
This was also what i've taken from the discussion on the SocketCAN ML.

I don't stick on the patch description. Would you like to produce a different
one? My Acked-by for the code remains sure :-)

Regards,
Oliver