On Wednesday 31 January 2007 11:27, Matthew Garrett wrote:

On Wed, Jan 31, 2007 at 12:13:04PM +0100, Andi Kleen wrote:

quoted

Matthew Garrett [off-list ref] writes:

quoted

PCI seems to require a delay of 10ms when sequencing from D3 to D0, 
which probably isn't acceptable latency for an "up" state.

It might be if the interface has been idle for some time
(and the delay is not busy looping of course)

Hm. How would this interact with receiving packets?

The hardware will hopefully have support to wake itself up when that 
happens.

-Andi