Re: Timeline of IPoIB performance
From: Grant Grundler <hidden>
Date: 2005-10-10 23:30:54
Possibly related (same subject, not in this thread)
- 2005-10-13 · Re: Timeline of IPoIB performance · Herbert Xu <herbert@gondor.apana.org.au>
- 2005-10-13 · Re: Timeline of IPoIB performance · Matt Leininger <hidden>
- 2005-10-12 · Re: Timeline of IPoIB performance · Matt Leininger <hidden>
- 2005-10-12 · Re: Timeline of IPoIB performance · Roland Dreier <hidden>
On Mon, Oct 10, 2005 at 02:26:52PM -0700, Grant Grundler wrote: ...
If it's interleaving, every other cacheline will be "local".
ISTR AMD64 was page-interleaved but then got confused by documents describing "128-bit" 2-way interleave. I now realize the 128bit is refering to interleave between two "banks" of memory behind each memory controller. ie 2 * 128-bit provides in the 32-byte cacheline size that most x86 programs expect. Anyway, I'm hoping that we'll see a consistent result if node interleave is turned off. sorry for the confusion, grant