On Wed, 2005-06-01 at 15:21 -0700, David S. Miller wrote:

From: "Michael Chan" <mchan@broadcom.com>
Date: Wed, 01 Jun 2005 13:33:39 -0700

quoted

I suppose we can enable interrupts in tg3_irq_quiesce() after setting
the SYNC bit.

Since the caller shuts down NAPI ->poll(), after setting the SYNC bit
we can just check the MAILBOX register, and if a '1' is there just
return.  Does one need to mask out the upper bits of the regiser in
order to avoid seeing the IRQ tag in such a comparison?

No, just check for the value 1 since that's the value we use to disable
interrupts. The value read back will always be 1 if 1 was previously
written to it.