On Thu, 21 Oct 2004 16:28:06 -0700
Jesse Barnes [off-list ref] wrote:
This patch originally from Greg Banks. Some parts of the tg3 driver depend on
PIO writes arriving in order. This patch ensures that in two key places
using the new mmiowb macro. This not only prevents bugs (the queues can be
corrupted), but is much faster than ensuring ordering using PIO reads (which
involve a few round trips to the target bus on some platforms).
Do other PCI systems which post PIO writes also potentially reorder
them just like this SGI system does? Just trying to get this situation
straight in my head.