On Tue, May 25, 2004 at 01:04:24PM -0700, Michael Chan wrote:

[...] A few years ago we saw cases where there were tx completions
on BDs that had not been sent. It turned out that on that machine, the
chipset was re-ordering the posted mmio writes to the send mailbox
register from 2 CPUs.[...]

On a related note, is there a good reason why the tg3 driver uses
the on-chip SRAM send ring by default instead of the host send ring?
This seems like it would dramatically increase the PIO load on the
chipset for some of the workloads I'm interested in.

Greg.
-- 
Greg Banks, R&D Software Engineer, SGI Australian Software Group.
I don't speak for SGI.