On Fri, Aug 27, 2021 at 09:59:56PM +0200, Thomas Gleixner wrote:

On Fri, Aug 27 2021 at 16:12, Vladimir Oltean wrote:

quoted

On Fri, Aug 27, 2021 at 01:01:35AM +0200, Thomas Gleixner wrote:

quoted

Even for the case where the regmap is not dealing with irq chips it does
not make any sense to protect low level operations on shared register
with a regular spinlock. I might be missing something though...

Mark, any comments?

Generally it is said that misusing raw spinlocks has detrimential
performance upon the real-time aspects of the system, and I don't really
have a good feeling for what constitutes misuse vs what is truly justified
(in fact I did start the thread with "apologies for my novice level of
understanding").

On the other hand, while it does seem a bit too much overhead for
sequences of MMIO reads/writes to be able to be preempted, it doesn't
sound like it would break something either, so...

The question is how long those sequences are.

If it's just a pair or so then the raw spinlock protection has
definitely a smaller worst case than the sleeping spinlock in the
contended case.

OTOH, if regmap operations consist of several dozens of MMIO accesses,
then the preempt disabled region might be quite long.

I'm not familiar enough with regmaps to make a judgement here.

I think "how long are the read/write regmap sequences" is outside of
regmap's control, but rather a matter of usage. This would point towards
the current solution, where users select whether to use raw spinlocks or
not, being the preferable one.