[tip: perf/urgent] perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest
From: tip-bot2 for Like Xu <hidden>
Date: 2021-08-05 09:34:33
Subsystem:
performance events subsystem, the rest, x86 architecture (32-bit and 64-bit) · Maintainers:
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Linus Torvalds, Thomas Gleixner, Borislav Petkov, Dave Hansen
The following commit has been merged into the perf/urgent branch of tip: Commit-ID: df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27 Gitweb: https://git.kernel.org/tip/df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27 Author: Like Xu [off-list ref] AuthorDate: Mon, 02 Aug 2021 15:08:50 +08:00 Committer: Peter Zijlstra [off-list ref] CommitterDate: Wed, 04 Aug 2021 15:16:34 +02:00 perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest If we use "perf record" in an AMD Milan guest, dmesg reports a #GP warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx: [] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20) [] Call Trace: [] amd_pmu_disable_event+0x22/0x90 [] x86_pmu_stop+0x4c/0xa0 [] x86_pmu_del+0x3a/0x140 The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host, while the guest perf driver should avoid such use. Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled") Signed-off-by: Like Xu <redacted> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Liam Merwick <redacted> Tested-by: Kim Phillips <redacted> Tested-by: Liam Merwick <redacted> Link: https://lkml.kernel.org/r/20210802070850.35295-1-likexu@tencent.com --- arch/x86/events/perf_event.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 2bf1c7e..2938c90 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h@@ -1115,9 +1115,10 @@ void x86_pmu_stop(struct perf_event *event, int flags); static inline void x86_pmu_disable_event(struct perf_event *event) { + u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask); struct hw_perf_event *hwc = &event->hw; - wrmsrl(hwc->config_base, hwc->config); + wrmsrl(hwc->config_base, hwc->config & ~disable_mask); if (is_counter_pair(hwc)) wrmsrl(x86_pmu_config_addr(hwc->idx + 1), 0);