quoted

From: Chancel Liu <redacted>

When the BCLK divider ratio is 1:1, fsl_sai_set_bclk() enables bypass
mode by setting BYP, but never clears the bit. The BYP=1 value remains
in the regcache, and is restored by regcache_sync() on the next
runtime resume.

Since BYP=1 combined with BCD=1 immediately outputs the ungated MCLK
as BCLK without waiting for BCE/TE/RE to be enabled, the clock is
driven prematurely before the stream is fully configured, causing
noise on some codecs.

Fix this by clearing BYP and BCI together in fsl_sai_config_disable().
Also clear BCI, which is programmed together with the bypass case in
synchronous mode, so the cached CR2 state is clean and regcache_sync()
will not restore bypass mode prematurely on the next resume.

Fixes: a50b7926d015 ("ASoC: fsl_sai: implement 1:1 bclk:mclk ratio
support")
Signed-off-by: Chancel Liu <redacted>

Reviewed-by: Shengjiu Wang <shengjiu.wang@gmail.com>

Thanks for your review. As sashiko reported this patch has potential
regression. I have to rework on it.

Regards, 
Chancel Liu

Best regards
Shengjiu Wang

quoted

---
 sound/soc/fsl/fsl_sai.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c index

9661602b53c5..4c0626d572a5 100644

--- a/sound/soc/fsl/fsl_sai.c
+++ b/sound/soc/fsl/fsl_sai.c

@@ -847,6 +847,9 @@ static void fsl_sai_config_disable(struct fsl_sai

*sai, int dir)

quoted

        regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx, ofs),
                           FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);

+       regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx, ofs),
+                          FSL_SAI_CR2_BCI | FSL_SAI_CR2_BYP, 0);
+
        /*
         * For sai master mode, after several open/close sai,
         * there will be no frame clock, and can't recover
--
2.50.1