Thread (17 messages) 17 messages, 8 authors, 2024-08-27

Re: [PATCH v2] powerpc: warn on emulation of dcbz instruction in kernel mode

From: Segher Boessenkool <hidden>
Date: 2024-08-23 19:32:43
Also in: lkml

Hi!

On Fri, Aug 23, 2024 at 03:54:59PM +0200, Christoph Hellwig wrote:
On Fri, Aug 23, 2024 at 08:06:00AM -0500, Segher Boessenkool wrote:
quoted
What does "uncached memory" even mean here?  Literally it would be
I=1 memory (uncachEABLE memory), but more likely you want M=0 memory
here ("non-memory memory", "not well-behaved memory", MMIO often).
Regular kernel memory vmapped with pgprot_noncached().
So, I=1 (and G=1).  Caching inhibited and guarded.  But M=1 (memory
coherence required) as with any other real memory :-)
quoted
If memset() is expected to be used with M=0, you cannot do any serious
optimisations to it at all.  If memset() is expected to be used with I=1
it should use a separate code path for it, probably the caller should
make the distinction.
DMA coherent memory which uses uncached memory for platforms that
do not provide hardware dma coherence can end up just about anywhere
in the kernel.  We could use special routines for a few places in
the DMA subsystem, but there might be plenty of others.
Yeah.  It will just be plenty slow, as we see here, that's what the
warning is for; but it works just fine :-)

The memset() code itself could chech for the storage attributes, but
that is probably more expensive than just assuming the happy case.
Maybe someone could try it out though!


Segher
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