Re: [PATCH v2 0/9] Introduce SMT level and add PowerPC support
From: Michael Ellerman <mpe@ellerman.id.au>
Date: 2023-06-29 11:10:54
Also in:
linux-arch, lkml
Sachin Sant [off-list ref] writes:
quoted
On 28-Jun-2023, at 3:35 PM, Laurent Dufour [off-list ref] wrote: I'm taking over the series Michael sent previously [1] which is smartly reviewing the initial series I sent [2]. This series is addressing the comments sent by Thomas and me on the Michael's one. Here is a short introduction to the issue this series is addressing: When a new CPU is added, the kernel is activating all its threads. This leads to weird, but functional, result when adding CPU on a SMT 4 system for instance. Here the newly added CPU 1 has 8 threads while the other one has 4 threads active (system has been booted with the 'smt-enabled=4' kernel option): ltcden3-lp12:~ # ppc64_cpu --info Core 0: 0* 1* 2* 3* 4 5 6 7 Core 1: 8* 9* 10* 11* 12* 13* 14* 15* This mixed SMT level may confused end users and/or some applications.Thanks for the patches Laurent. Is the SMT level retained even when dynamically changing SMT values? I am observing difference in behaviour with and without smt-enabled kernel command line option. When smt-enabled= option is specified SMT level is retained across cpu core remove and add. Without this option but changing SMT level during runtime using ppc64_cpu —smt=<level>, the SMT level is not retained after cpu core add.
That's because ppc64_cpu is not using the sysfs SMT control file, it's just onlining/offlining threads manually. If you run: $ ppc64_cpu --smt=4 And then also do: $ echo 4 > /sys/devices/system/cpu/smt/control It should work as expected? ppc64_cpu will need to be updated to do that automatically. cheers