Re: [PATCH v7 1/7] powerpc/pmem: Restrict papr_scm to P8 and above.

Michal Suchánek [off-list ref] writes:

Hello,

On Wed, Jul 01, 2020 at 12:52:29PM +0530, Aneesh Kumar K.V wrote:

quoted

The PAPR based virtualized persistent memory devices are only supported on
POWER9 and above. In the followup patch, the kernel will switch the persistent
memory cache flush functions to use a new `dcbf` variant instruction. The new
instructions even though added in ISA 3.1 works even on P8 and P9 because these
are implemented as a variant of existing `dcbf` and `hwsync` and on P8 and
P9 behaves as such.

Considering these devices are only supported on P8 and above,  update the driver
to prevent a P7-compat guest from using persistent memory devices.

We don't update of_pmem driver with the same condition, because, on bare-metal,
the firmware enables pmem support only on P9 and above. There the kernel depends
on OPAL firmware to restrict exposing persistent memory related device tree
entries on older hardware. of_pmem.ko is written without any arch dependency and
we don't want to add ppc64 specific cpu feature check in of_pmem driver.

Signed-off-by: Aneesh Kumar K.V <redacted>
---
 arch/powerpc/platforms/pseries/pmem.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/powerpc/platforms/pseries/pmem.c b/arch/powerpc/platforms/pseries/pmem.c
index f860a897a9e0..2347e1038f58 100644
--- a/arch/powerpc/platforms/pseries/pmem.c
+++ b/arch/powerpc/platforms/pseries/pmem.c

@@ -147,6 +147,12 @@ const struct of_device_id drc_pmem_match[] = {
 
 static int pseries_pmem_init(void)
 {
+	/*
+	 * Only supported on POWER8 and above.
+	 */
+	if (!cpu_has_feature(CPU_FTR_ARCH_207S))
+		return 0;
+

This looks superfluous.

The hypervisor is responsible for publishing the pmem in devicetree when
present, kernel is responsible for using it when supported by the
kernel.

Or is there a problem that the flush instruction is not available in P7
compat mode?

We want to avoid the usage of persistent memory on p7 compat mode
because such a guest can LPM migrate to p7 systems. Now ideally I would
expect hypervisor to avoid such migration, that is a p7 compat mode
guest running on p10 using persistence memory migrating to p7
(considering p7 never really had support for persistent memory).

There was also the complexity w.r.t what instructions the userspace will
use. So it was discussed at that point that we could comfortably state
and prevent the usage of persistent memory on p7 and below. 

Even then volatile regions should still work.

That is a different problem altogether. We could really kill the usage of
cache flush w.r.t volatile regions from the nvdimm driver right? 

For all these reason, disabling pmem on p7 was found to be the simplest solution. 

-aneesh