Re: [PATCH 1/3] perf: Add macros to specify onchip L2/L3 accesses

Peter Zijlstra [off-list ref] writes:

On Tue, Sep 14, 2021 at 08:40:38PM +1000, Michael Ellerman wrote:

quoted

Peter Zijlstra [off-list ref] writes:

quoted

quoted

I'm thinking we ought to keep hops as steps along the NUMA fabric, with
0 hops being the local node. That only gets us:

 L2, remote=0, hops=HOPS_0 -- our L2
 L2, remote=1, hops=HOPS_0 -- L2 on the local node but not ours
 L2, remote=1, hops!=HOPS_0 -- L2 on a remote node

Hmm. I'm not sure about tying it directly to NUMA hops. I worry we're
going to see more and more systems where there's a hierarchy within the
chip/package, in addition to the traditional NUMA hierarchy.

Although then I guess it becomes a question of what exactly is a NUMA
hop, maybe the answer is that on those future systems those
intra-chip/package hops should be represented as NUMA hops.

It's not like we have a hard definition of what a NUMA hop is?

Not really, typically whatever the BIOS/DT/whatever tables tell us. I
think in case of Power you're mostly making things up in software :-)

Firmware is software so yes :)

But yeah, I think we have plenty wriggle room there.

OK.

cheers