Patch set adds PMU registers namely Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
in PowerPC. These registers provides the instruction/data address and
adding these to extended regs helps in debug purposes.
Patch 1/2 adds SIAR and SDAR as part of the extended regs mask.
Patch 2/2 includes perf tools side changes to add the SPRs to
sample_reg_mask to use with -I? option.
Athira Rajeev (2):
powerpc/perf: Expose instruction and data address registers as part of
extended regs
tools/perf: Add perf tools support to expose instruction and data
address registers as part of extended regs
arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
arch/powerpc/perf/perf_regs.c | 4 ++++
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
tools/perf/arch/powerpc/include/perf_regs.h | 2 ++
tools/perf/arch/powerpc/util/perf_regs.c | 2 ++
5 files changed, 22 insertions(+), 10 deletions(-)
--
1.8.3.1
Patch enables presenting of Sampled Instruction Address Register (SIAR)
and Sampled Data Address Register (SDAR) SPRs as part of extended regsiters
for perf tool. Add these SPR's to sample_reg_mask in the tool side (to use
with -I? option).
Signed-off-by: Athira Rajeev <redacted>
---
tools/arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
tools/perf/arch/powerpc/include/perf_regs.h | 2 ++
tools/perf/arch/powerpc/util/perf_regs.c | 2 ++
3 files changed, 11 insertions(+), 5 deletions(-)
@@ -61,6 +61,8 @@ enum perf_event_powerpc_regs {PERF_REG_POWERPC_PMC4,PERF_REG_POWERPC_PMC5,PERF_REG_POWERPC_PMC6,+PERF_REG_POWERPC_SDAR,+PERF_REG_POWERPC_SIAR,/* Max regs without the extended regs */PERF_REG_POWERPC_MAX=PERF_REG_POWERPC_MMCRA+1,};
Patch adds support to include Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
PERF_REG_EXTENDED_MAX to include these SPR's.
Signed-off-by: Athira Rajeev <redacted>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
arch/powerpc/perf/perf_regs.c | 4 ++++
2 files changed, 11 insertions(+), 5 deletions(-)
@@ -61,6 +61,8 @@ enum perf_event_powerpc_regs {PERF_REG_POWERPC_PMC4,PERF_REG_POWERPC_PMC5,PERF_REG_POWERPC_PMC6,+PERF_REG_POWERPC_SDAR,+PERF_REG_POWERPC_SIAR,/* Max regs without the extended regs */PERF_REG_POWERPC_MAX=PERF_REG_POWERPC_MMCRA+1,};
Patch set adds PMU registers namely Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
in PowerPC. These registers provides the instruction/data address and
adding these to extended regs helps in debug purposes.
Patch 1/2 adds SIAR and SDAR as part of the extended regs mask.
Patch 2/2 includes perf tools side changes to add the SPRs to
sample_reg_mask to use with -I? option.
Athira Rajeev (2):
powerpc/perf: Expose instruction and data address registers as part of
extended regs
tools/perf: Add perf tools support to expose instruction and data
address registers as part of extended regs
Tested with the following scenarios on P9, P10 - PowerVM environment
1. perf record -I? - shows added - sdar, siar
2. perf record -I <workload> and perf report -D - shows added - sdar, siar with and with out counts.
Tested-by: Nageswara R Sastry <redacted>
Patch set adds PMU registers namely Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
in PowerPC. These registers provides the instruction/data address and
adding these to extended regs helps in debug purposes.
Patch 1/2 adds SIAR and SDAR as part of the extended regs mask.
Patch 2/2 includes perf tools side changes to add the SPRs to
sample_reg_mask to use with -I? option.
Athira Rajeev (2):
powerpc/perf: Expose instruction and data address registers as part of
extended regs
tools/perf: Add perf tools support to expose instruction and data
address registers as part of extended regs
Patchset looks good to me.
Reviewed-By: kajol Jain<redacted>
Thanks,
Kajol Jain
On 02-Sep-2021, at 1:04 PM, kajoljain [off-list ref] wrote:
On 6/20/21 8:15 PM, Athira Rajeev wrote:
quoted
Patch set adds PMU registers namely Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
in PowerPC. These registers provides the instruction/data address and
adding these to extended regs helps in debug purposes.
Patch 1/2 adds SIAR and SDAR as part of the extended regs mask.
Patch 2/2 includes perf tools side changes to add the SPRs to
sample_reg_mask to use with -I? option.
Athira Rajeev (2):
powerpc/perf: Expose instruction and data address registers as part of
extended regs
tools/perf: Add perf tools support to expose instruction and data
address registers as part of extended regs
Patchset looks good to me.
Reviewed-By: kajol Jain<redacted>
Hi Arnaldo,
Requesting for your review on this patchset.
Thanks
Athira
From: Michael Ellerman <mpe@ellerman.id.au> Date: 2021-09-08 05:18:00
Athira Rajeev [off-list ref] writes:
Patch adds support to include Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
PERF_REG_EXTENDED_MAX to include these SPR's.
Signed-off-by: Athira Rajeev <redacted>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
arch/powerpc/perf/perf_regs.c | 4 ++++
2 files changed, 11 insertions(+), 5 deletions(-)
This file is built for all powerpc configs that have PERF_EVENTS. Which
includes CPUs that don't have SDAR or SIAR.
Don't we need checks in perf_reg_value() like we do for SIER?
I guess we already got this wrong when we added the Power10 registers,
SIER2/3 etc.
cheers
On 08-Sep-2021, at 10:47 AM, Michael Ellerman [off-list ref] wrote:
Athira Rajeev [off-list ref] writes:
quoted
Patch adds support to include Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
PERF_REG_EXTENDED_MAX to include these SPR's.
Signed-off-by: Athira Rajeev <redacted>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
arch/powerpc/perf/perf_regs.c | 4 ++++
2 files changed, 11 insertions(+), 5 deletions(-)
return mfspr(SPRN_SIER2);
case PERF_REG_POWERPC_SIER3:
return mfspr(SPRN_SIER3);
+ case PERF_REG_POWERPC_SDAR:
+ return mfspr(SPRN_SDAR);
#endif
+ case PERF_REG_POWERPC_SIAR:
+ return mfspr(SPRN_SIAR);
default: return 0;
}
This file is built for all powerpc configs that have PERF_EVENTS. Which
includes CPUs that don't have SDAR or SIAR.
Don't we need checks in perf_reg_value() like we do for SIER?
Hi Michael,
Thanks for the review.
SIER is part of PERF_REG_PMU_MASK and hence check is needed to see if platform supports SIER.
Incase of extended regs, they are part of PERF_REG_EXTENDED_MASK and this mask is
filled with supported registers while registering the PMU ( ie during init_power9/10_pmu ). So these registers will be added
only for supported platforms. The validity of extended mask is also done in PMU common code
( In kernel/events/core.c with PERF_REG_EXTENDED_MASK check ). So an unsupported platform requesting for extended
registers won’t get it.
Thanks
Athira
I guess we already got this wrong when we added the Power10 registers,
SIER2/3 etc.
cheers
From: Arnaldo Carvalho de Melo <acme@kernel.org> Date: 2021-09-11 19:10:14
Em Mon, Sep 06, 2021 at 08:13:13AM +0530, Athira Rajeev escreveu:
quoted
On 02-Sep-2021, at 1:04 PM, kajoljain [off-list ref] wrote:
On 6/20/21 8:15 PM, Athira Rajeev wrote:
quoted
Patch set adds PMU registers namely Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
in PowerPC. These registers provides the instruction/data address and
adding these to extended regs helps in debug purposes.
Patch 1/2 adds SIAR and SDAR as part of the extended regs mask.
Patch 2/2 includes perf tools side changes to add the SPRs to
sample_reg_mask to use with -I? option.
Athira Rajeev (2):
powerpc/perf: Expose instruction and data address registers as part of
extended regs
tools/perf: Add perf tools support to expose instruction and data
address registers as part of extended regs
Patchset looks good to me.
Reviewed-By: kajol Jain<redacted>
Hi Arnaldo,
Requesting for your review on this patchset.
So, this touches the kernel, usually I get a patchkit when the kernel
bits landed, is that the case by now?
- Arnaldo
From: Michael Ellerman <mpe@ellerman.id.au> Date: 2021-09-20 06:55:15
Arnaldo Carvalho de Melo [off-list ref] writes:
Em Mon, Sep 06, 2021 at 08:13:13AM +0530, Athira Rajeev escreveu:
quoted
quoted
On 02-Sep-2021, at 1:04 PM, kajoljain [off-list ref] wrote:
On 6/20/21 8:15 PM, Athira Rajeev wrote:
quoted
Patch set adds PMU registers namely Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) as part of extended regs
in PowerPC. These registers provides the instruction/data address and
adding these to extended regs helps in debug purposes.
Patch 1/2 adds SIAR and SDAR as part of the extended regs mask.
Patch 2/2 includes perf tools side changes to add the SPRs to
sample_reg_mask to use with -I? option.
Athira Rajeev (2):
powerpc/perf: Expose instruction and data address registers as part of
extended regs
tools/perf: Add perf tools support to expose instruction and data
address registers as part of extended regs
Patchset looks good to me.
Reviewed-By: kajol Jain<redacted>
Hi Arnaldo,
Requesting for your review on this patchset.
So, this touches the kernel, usually I get a patchkit when the kernel
bits landed, is that the case by now?
Not yet, I'd like some changes to the kernel patch.
cheers
From: Michael Ellerman <mpe@ellerman.id.au> Date: 2021-09-20 07:14:00
Athira Rajeev [off-list ref] writes:
quoted
On 08-Sep-2021, at 10:47 AM, Michael Ellerman [off-list ref] wrote:
Athira Rajeev [off-list ref] writes:
quoted
Patch adds support to include Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
PERF_REG_EXTENDED_MAX to include these SPR's.
Signed-off-by: Athira Rajeev <redacted>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
arch/powerpc/perf/perf_regs.c | 4 ++++
2 files changed, 11 insertions(+), 5 deletions(-)
return mfspr(SPRN_SIER2);
case PERF_REG_POWERPC_SIER3:
return mfspr(SPRN_SIER3);
+ case PERF_REG_POWERPC_SDAR:
+ return mfspr(SPRN_SDAR);
#endif
+ case PERF_REG_POWERPC_SIAR:
+ return mfspr(SPRN_SIAR);
default: return 0;
}
This file is built for all powerpc configs that have PERF_EVENTS. Which
includes CPUs that don't have SDAR or SIAR.
Don't we need checks in perf_reg_value() like we do for SIER?
Hi Michael,
Thanks for the review.
SIER is part of PERF_REG_PMU_MASK and hence check is needed to see if platform supports SIER.
Incase of extended regs, they are part of PERF_REG_EXTENDED_MASK and this mask is
filled with supported registers while registering the PMU ( ie during init_power9/10_pmu ). So these registers will be added
only for supported platforms. The validity of extended mask is also done in PMU common code
( In kernel/events/core.c with PERF_REG_EXTENDED_MASK check ). So an unsupported platform requesting for extended
registers won’t get it.
Right, I'd forgotten how that works.
But I think part of the reason I didn't remember is that
PERF_REG_PMU_MASK_31 doesn't mention those regs by name, it's just a hex
constant, ie:
-#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0)
+#define PERF_REG_PMU_MASK_31 (0x3fffULL << PERF_REG_POWERPC_MMCR0)
Presumably you tested that the added 0x3 there sets the right bits for
SDAR and SIAR, but it's 1) not obvious and 2) fragile.
So I'd like it better if we constructed the PERF_REG_PMU_MASK_31, and
other similar masks, by or'ing together the actual register value
constants.
eg. something like:
#define PERF_REG_PMU_MASK_31 \
((1ul << PERF_REG_POWERPC_MMCR0) | (1ul << PERF_REG_POWERPC_MMCR1) | \
(1ul << PERF_REG_POWERPC_MMCR2) | (1ul << PERF_REG_POWERPC_MMCR3) | \
(1ul << PERF_REG_POWERPC_SIER2) | (1ul << PERF_REG_POWERPC_SIER3) | \
(1ul << PERF_REG_POWERPC_PMC1) | (1ul << PERF_REG_POWERPC_PMC2) | \
(1ul << PERF_REG_POWERPC_PMC3) | (1ul << PERF_REG_POWERPC_PMC4) | \
(1ul << PERF_REG_POWERPC_PMC5) | (1ul << PERF_REG_POWERPC_PMC6))
Also PERF_REG_EXTENDED_MAX should be part of the enum, just like
PERF_REG_POWERPC_MAX.
cheers
On 20-Sep-2021, at 12:43 PM, Michael Ellerman [off-list ref] wrote:
Athira Rajeev [off-list ref] writes:
quoted
quoted
On 08-Sep-2021, at 10:47 AM, Michael Ellerman [off-list ref] wrote:
Athira Rajeev [off-list ref] writes:
quoted
Patch adds support to include Sampled Instruction Address Register
(SIAR) and Sampled Data Address Register (SDAR) SPRs as part of extended
registers. Update the definition of PERF_REG_PMU_MASK_300/31 and
PERF_REG_EXTENDED_MAX to include these SPR's.
Signed-off-by: Athira Rajeev <redacted>
---
arch/powerpc/include/uapi/asm/perf_regs.h | 12 +++++++-----
arch/powerpc/perf/perf_regs.c | 4 ++++
2 files changed, 11 insertions(+), 5 deletions(-)
return mfspr(SPRN_SIER2);
case PERF_REG_POWERPC_SIER3:
return mfspr(SPRN_SIER3);
+ case PERF_REG_POWERPC_SDAR:
+ return mfspr(SPRN_SDAR);
#endif
+ case PERF_REG_POWERPC_SIAR:
+ return mfspr(SPRN_SIAR);
default: return 0;
}
This file is built for all powerpc configs that have PERF_EVENTS. Which
includes CPUs that don't have SDAR or SIAR.
Don't we need checks in perf_reg_value() like we do for SIER?
Hi Michael,
Thanks for the review.
SIER is part of PERF_REG_PMU_MASK and hence check is needed to see if platform supports SIER.
Incase of extended regs, they are part of PERF_REG_EXTENDED_MASK and this mask is
filled with supported registers while registering the PMU ( ie during init_power9/10_pmu ). So these registers will be added
only for supported platforms. The validity of extended mask is also done in PMU common code
( In kernel/events/core.c with PERF_REG_EXTENDED_MASK check ). So an unsupported platform requesting for extended
registers won’t get it.
Right, I'd forgotten how that works.
But I think part of the reason I didn't remember is that
PERF_REG_PMU_MASK_31 doesn't mention those regs by name, it's just a hex
constant, ie:
-#define PERF_REG_PMU_MASK_31 (0xfffULL << PERF_REG_POWERPC_MMCR0)
+#define PERF_REG_PMU_MASK_31 (0x3fffULL << PERF_REG_POWERPC_MMCR0)
Presumably you tested that the added 0x3 there sets the right bits for
SDAR and SIAR, but it's 1) not obvious and 2) fragile.
So I'd like it better if we constructed the PERF_REG_PMU_MASK_31, and
other similar masks, by or'ing together the actual register value
constants.
eg. something like:
#define PERF_REG_PMU_MASK_31 \
((1ul << PERF_REG_POWERPC_MMCR0) | (1ul << PERF_REG_POWERPC_MMCR1) | \
(1ul << PERF_REG_POWERPC_MMCR2) | (1ul << PERF_REG_POWERPC_MMCR3) | \
(1ul << PERF_REG_POWERPC_SIER2) | (1ul << PERF_REG_POWERPC_SIER3) | \
(1ul << PERF_REG_POWERPC_PMC1) | (1ul << PERF_REG_POWERPC_PMC2) | \
(1ul << PERF_REG_POWERPC_PMC3) | (1ul << PERF_REG_POWERPC_PMC4) | \
(1ul << PERF_REG_POWERPC_PMC5) | (1ul << PERF_REG_POWERPC_PMC6))
Also PERF_REG_EXTENDED_MAX should be part of the enum, just like
PERF_REG_POWERPC_MAX.
Sure Michael,
I will address these changes in next version
Thanks
Athira