[PATCH v2 0/2] powerpc/sstep: Add emulation support and tests for 'setb' instruction

This patchset adds emulation support and tests for setb instruction.
Test cases are written to test different CR fields with different
bits set in each field.

v1->v2:
  - Extract all the bits of the CR field (bfa) and check if the
    LT, GT bits of that CR field (bfa) are set.
  - Place 'setb' emulation code after 'mfcr' instruction emulation.
  - Add 'cpu_feature' in the selftests patch to restrict them to ISA v3.0

Sathvika Vasireddy (2):
  powerpc/sstep: Add emulation support for ‘setb’ instruction
  powerpc/sstep: Add tests for setb instruction

 arch/powerpc/include/asm/ppc-opcode.h |  1 +
 arch/powerpc/lib/sstep.c              | 22 ++++++++++++++++++++++
 arch/powerpc/lib/test_emulate_step.c  | 29 +++++++++++++++++++++++++++++
 3 files changed, 52 insertions(+)

-- 
2.16.4

This adds emulation support for the following instruction:
   * Set Boolean (setb)

Signed-off-by: Sathvika Vasireddy <redacted>
---
 arch/powerpc/lib/sstep.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/powerpc/lib/sstep.c b/arch/powerpc/lib/sstep.c
index 45bda2520755..aee42bcc775b 100644
--- a/arch/powerpc/lib/sstep.c
+++ b/arch/powerpc/lib/sstep.c

@@ -1700,6 +1700,28 @@ int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
 			op->val = regs->ccr & imm;
 			goto compute_done;
 
+		case 128:	/* setb */
+			if (!cpu_has_feature(CPU_FTR_ARCH_300))
+				goto unknown_opcode;
+			/*
+			 * 'ra' encodes the CR field number (bfa) in the top 3 bits.
+			 * Since each CR field is 4 bits,
+			 * we can simply mask off the bottom two bits (bfa * 4)
+			 * to yield the first bit in the CR field.
+			 */
+			ra = ra & ~0x3;
+			/* 'val' stores bits of the CR field (bfa) */
+			val = regs->ccr >> (CR0_SHIFT - ra);
+			/* checks if the LT bit of CR field (bfa) is set */
+			if (val & 8)
+				op->val = -1;
+			/* checks if the GT bit of CR field (bfa) is set */
+			else if (val & 4)
+				op->val = 1;
+			else
+				op->val = 0;
+			goto compute_done;
+
 		case 144:	/* mtcrf */
 			op->type = COMPUTE + SETCC;
 			imm = 0xf0000000UL;

-- 
2.16.4

This adds selftests for setb instruction.

Signed-off-by: Sathvika Vasireddy <redacted>
---
 arch/powerpc/include/asm/ppc-opcode.h |  1 +
 arch/powerpc/lib/test_emulate_step.c  | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index ac41776661e9..927551dd870b 100644
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h

@@ -245,6 +245,7 @@
 #define PPC_INST_STRING			0x7c00042a
 #define PPC_INST_STRING_MASK		0xfc0007fe
 #define PPC_INST_STRING_GEN_MASK	0xfc00067e
+#define PPC_INST_SETB			0x7c000100
 #define PPC_INST_STSWI			0x7c0005aa
 #define PPC_INST_STSWX			0x7c00052a
 #define PPC_INST_TRECHKPT		0x7c0007dd

diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c
index 783d1b85ecfe..a0a52fe5e979 100644
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c

@@ -53,6 +53,8 @@
 	ppc_inst_prefix(PPC_PREFIX_MLS | __PPC_PRFX_R(pr) | IMM_H(i), \
 			PPC_RAW_ADDI(t, a, i))
 
+#define TEST_SETB(t, bfa)       ppc_inst(PPC_INST_SETB | ___PPC_RT(t) | ___PPC_RA((bfa & 0x7) << 2))
+
 
 static void __init init_pt_regs(struct pt_regs *regs)
 {

@@ -929,6 +931,33 @@ static struct compute_test compute_tests[] = {
 			}
 		}
 	},
+	{
+		.mnemonic = "setb",
+		.cpu_feature = CPU_FTR_ARCH_300,
+		.subtests = {
+			{
+				.descr = "BFA = 1, CR = GT",
+				.instr = TEST_SETB(20, 1),
+				.regs = {
+					.ccr = 0x4000000,
+				}
+			},
+			{
+				.descr = "BFA = 4, CR = LT",
+				.instr = TEST_SETB(20, 4),
+				.regs = {
+					.ccr = 0x8000,
+				}
+			},
+			{
+				.descr = "BFA = 5, CR = EQ",
+				.instr = TEST_SETB(20, 5),
+				.regs = {
+					.ccr = 0x200,
+				}
+			}
+		}
+	},
 	{
 		.mnemonic = "add",
 		.subtests = {

-- 
2.16.4

On Tue, May 11, 2021 at 07:18:32AM -0500, Sathvika Vasireddy wrote:

This adds emulation support for the following instruction:
   * Set Boolean (setb)

Signed-off-by: Sathvika Vasireddy <redacted>

This looks fine to me, thanks!

Reviewed-by: Segher Boessenkool <redacted>


Segher

Sathvika Vasireddy wrote:

This adds emulation support for the following instruction:
   * Set Boolean (setb)

Signed-off-by: Sathvika Vasireddy <redacted>
---
 arch/powerpc/lib/sstep.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Tested-by: Naveen N. Rao <redacted>

Sathvika Vasireddy wrote:

This adds selftests for setb instruction.

Signed-off-by: Sathvika Vasireddy <redacted>
---
 arch/powerpc/include/asm/ppc-opcode.h |  1 +
 arch/powerpc/lib/test_emulate_step.c  | 29 +++++++++++++++++++++++++++++
 2 files changed, 30 insertions(+)

Tested-by: Naveen N. Rao <redacted>

On 11/05/21 5:48 pm, Sathvika Vasireddy wrote:

This adds emulation support for the following instruction:
   * Set Boolean (setb)

Signed-off-by: Sathvika Vasireddy <redacted>
---
 arch/powerpc/lib/sstep.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

LGTM.

Reviewed-by: Sandipan Das <redacted>

On Tue, 11 May 2021 07:18:31 -0500, Sathvika Vasireddy wrote:

This patchset adds emulation support and tests for setb instruction.
Test cases are written to test different CR fields with different
bits set in each field.

v1->v2:
  - Extract all the bits of the CR field (bfa) and check if the
    LT, GT bits of that CR field (bfa) are set.
  - Place 'setb' emulation code after 'mfcr' instruction emulation.
  - Add 'cpu_feature' in the selftests patch to restrict them to ISA v3.0

[...]

Applied to powerpc/next.

[1/2] powerpc/sstep: Add emulation support for ‘setb’ instruction
      https://git.kernel.org/powerpc/c/5b75bd763d369e43e6d09e85eaea22fde37c0e89
[2/2] powerpc/sstep: Add tests for setb instruction
      https://git.kernel.org/powerpc/c/60060d704c55a9450208b8f0bc5026df9d4ab1d6

cheers