Thread (55 messages) 55 messages, 11 authors, 2021-05-24

Re: [PATCH v5 5/9] powerpc/mm/book3s64: Update tlb flush routines to take a page walk cache flush argument

From: Guenter Roeck <linux@roeck-us.net>
Date: 2021-05-15 23:05:08
Also in: linux-mm

On 5/15/21 1:41 PM, Andrew Morton wrote:
On Sat, 15 May 2021 09:35:25 -0700 Guenter Roeck [off-list ref] wrote:
quoted
quoted
  
  #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
  static inline void flush_pmd_tlb_range(struct vm_area_struct *vma,
                  ^^^^
quoted
  				       unsigned long start, unsigned long end)
+{
+	return flush_pmd_tlb_pwc_range(vma, start, end, false);
         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

Doesn't that cause build warnings/errors all over the place ?
It will, thanks.  I queued a fix.
Also in mm/mremap.c, in case you didn't see it:

#ifndef flush_pte_tlb_pwc_range
#define flush_pte_tlb_pwc_range flush_pte_tlb_pwc_range
static inline void flush_pte_tlb_pwc_range(struct vm_area_struct *vma,
               ^^^^
                                            unsigned long start,
                                            unsigned long end)
{
         return flush_tlb_range(vma, start, end);
         ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
}
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