On 2021/03/04 09:45AM, Segher Boessenkool wrote:

On Wed, Mar 03, 2021 at 10:01:27PM +0530, Naveen N. Rao wrote:

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On 2021/03/01 08:37PM, Segher Boessenkool wrote:

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And, r6 always ends up with 0xaea. It changes with the value I put into 
r6 though.

That is exactly the behaviour specified for p8.  0aaa+0040=0aea.

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Granted, this is all up in the air, but it does look like there is more 
going on and the value isn't the EA or the value at the address.

That *is* the EA.  The EA is the address the insn does the access at.

I'm probably missing something here. 0xaaa is the value I stored at an 
offset of 64 bytes from the stack pointer (r1 is copied into r6). In the 
ldu instruction above, the EA is 64(r6), which should translate to 
r1+64.  The data returned by the load would be 0xaaa, which should be 
discarded per the description you provided above. So, I would expect to 
see a 0xc0.. address in r6.

Yes, I misread your code it seems.

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In fact, this looks to be the behavior documented for P9:

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Power9 does:

  Load with Update Instructions (RA = 0)
    EA is placed into R0.
  Load with Update Instructions (RA = RT)
    The storage operand addressed by EA is accessed. The 
    displacement
    field is added to the data returned by the load and placed into 
    RT.

Yup.  So on what cpu did you test?

I tested this on two processors:
2.0 (pvr 004d 0200)
2.1 (pvr 004b 0201)

I guess the behavior changed some time during P8, but I don't have a P9 
to test this on.

In any case, this souldn't matter too much for us as you rightly point 
out:

Either way, the kernel should not emulate any particular cpu here, I'd
say, esp. since recent cpus do different things for this invalid form.

Ack.


Thanks!
- Naveen