[PATCH 02/30] altera-msgdma.c: Couple of typos fixed
From: Bhaskar Chowdhury <hidden>
Date: 2021-03-28 23:56:42
Also in:
dmaengine, dri-devel, linux-iommu, lkml
Subsystem:
altera msgdma ip core driver, dma generic offload engine subsystem, the rest · Maintainers:
Olivier Dautricourt, Vinod Koul, Linus Torvalds
s/assosiated/associated/ s/oder/order/ Signed-off-by: Bhaskar Chowdhury <redacted> --- drivers/dma/altera-msgdma.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/altera-msgdma.c b/drivers/dma/altera-msgdma.c
index 9a841ce5f0c5..c3483bf2aaa7 100644
--- a/drivers/dma/altera-msgdma.c
+++ b/drivers/dma/altera-msgdma.c@@ -152,7 +152,7 @@ struct msgdma_extended_desc { /** * struct msgdma_sw_desc - implements a sw descriptor * @async_tx: support for the async_tx api - * @hw_desc: assosiated HW descriptor + * @hw_desc: associated HW descriptor * @node: node to move from the free list to the tx list * @tx_list: transmit list node */
@@ -510,7 +510,7 @@ static void msgdma_copy_one(struct msgdma_device *mdev, * of the DMA controller. The descriptor will get flushed to the * FIFO, once the last word (control word) is written. Since we * are not 100% sure that memcpy() writes all word in the "correct" - * oder (address from low to high) on all architectures, we make + * order (address from low to high) on all architectures, we make * sure this control word is written last by single coding it and * adding some write-barriers here. */ --
2.26.3