Excerpts from Christophe Leroy's message of January 27, 2021 6:54 pm:

Le 25/02/2020 à 18:35, Nicholas Piggin a écrit :

quoted

Implement the bulk of interrupt return logic in C. The asm return code
must handle a few cases: restoring full GPRs, and emulating stack store.

The stack store emulation is significantly simplfied, rather than creating
a new return frame and switching to that before performing the store, it
uses the PACA to keep a scratch register around to perform thestore.

The asm return code is moved into 64e for now. The new logic has made
allowance for 64e, but I don't have a full environment that works well
to test it, and even booting in emulated qemu is not great for stress
testing. 64e shouldn't be too far off working with this, given a bit
more testing and auditing of the logic.

This is slightly faster on a POWER9 (page fault speed increases about
1.1%), probably due to reduced mtmsrd.

How do you measure 'page fault' speed ?

mmap 1000 pages, store to each one, mprotect(PROT_READ) then 
mprotect(PROT_READ|PROT_WRITE), then store a byte to each page
and measure the cost. Something like that IIRC.

Thanks,
Nick