Christophe Leroy [off-list ref] writes:

Le 21/10/2020 à 10:53, Madhavan Srinivasan a écrit :

quoted

In power10 DD1, there is an issue where the
Sampled Instruction Address Register (SIAR)
not latching to the sampled address during
random sampling. This results in value of 0s
in the SIAR. Patch adds a check to use regs->nip
when SIAR is zero.

Why not use regs->nip at all time in that case, and not read SPRN_SIAR at all ?

Yeah that's a reasonable question.

I can't really find anywhere in the ISA that explains it.

I believe the main (or only?) reason is that interrupts might be
disabled when the PMU samples the instruction. So in that case the SIAR
will point at an instruction somewhere in interrupts-off code, whereas
the NIP will point to the location where we re-enabled interrupts and
took the PMU interrupt.

cheers