Thread (9 messages) 9 messages, 3 authors, 2019-12-18

Re: [PATCH v2 2/3] mm/mmu_gather: Invalidate TLB correctly on batch allocation failure and flush

From: Peter Zijlstra <peterz@infradead.org>
Date: 2019-12-18 14:15:36
Also in: linux-arch, linux-mm, lkml

On Thu, Dec 19, 2019 at 12:13:48AM +1100, Michael Ellerman wrote:
quoted
quoted
I'm a little confused though; if nohash is a software TLB fill, why do
you need a TLBI for tables?
nohash (AKA book3e) has different mmu modes. I don't follow all the 
details w.r.t book3e. Paul or Michael might be able to explain the need 
for table flush with book3e.
Some of the Book3E CPUs have a partial hardware table walker. The IBM one (A2)
did, before we ripped that support out. And the Freescale (NXP) e6500
does, see eg:

  28efc35fe68d ("powerpc/e6500: TLB miss handler with hardware tablewalk support")

They only support walking one level IIRC, ie. you can create a TLB entry
that points to a PTE page, and the hardware will dereference that to get
a PTE and load that into the TLB.
Shiny!, all the embedded goodness. Thanks for the info.
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help