Re: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit property in EP driver.

On Mon, Aug 12, 2019 at 10:39:00AM +0000, Xiaowei Bao wrote:

quoted

-----Original Message-----
From: Lorenzo Pieralisi <redacted>
Sent: 2019年8月12日 18:12
To: Xiaowei Bao <redacted>; kishon@ti.com
Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
shawnguo@kernel.org; Leo Li [off-list ref]; arnd@arndb.de;
gregkh@linuxfoundation.org; M.h. Lian [off-list ref]; Mingkai
Hu [off-list ref]; Roy Zang [off-list ref];
kstewart@linuxfoundation.org; pombredanne@nexb.com;
shawn.lin@rock-chips.com; linux-pci@vger.kernel.org;
devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
Subject: [EXT] Re: [PATCHv3 1/2] PCI: layerscape: Add the bar_fixed_64bit
property in EP driver.

Caution: EXT Email

First off:

Trim the CC list, you CC'ed maintainers (and mailing lists) for no reasons
whatsover.

[Xiaowei Bao]Hi Lorenzo, I am not clear why the mail list is the CC, I use the command "git send-email --to", I will try to send the patch again, do I need to modify the version is v4 when I send this patch again?

Yes you do.

Wrap lines to max 80 characters. There is no need to add [Xiaowei Bao].

1) Read, email etiquette

https://kernelnewbies.org/PatchCulture

2) get_maintainer.pl -f drivers/pci/controller/dwc/pci-layerscape.c

Compare the output to the people in CC, trim it accordingly.

3) The NXP maintainers in the MAINTAINERS file have not given a single
   comment for this patchset. Either they show up or I will remove them
   from the MAINTAINERS list.

4) Before submitting patches, talk to someone at NXP who can help you
   format them in preparation for posting, I do not have time to write
   guidelines for everyone posting on linux-pci, sorry, the information
   is out there if you care to read it.

Thanks,
Lorenzo

quoted

Then, read this:

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Flore.ke
rnel.org%2Flinux-pci%2F20171026223701.GA25649%40bhelgaas-glaptop.roa
m.corp.google.com%2F&data=02%7C01%7Cxiaowei.bao%40nxp.com%7
C1c586178e23c423a0e8808d71f0d8f6f%7C686ea1d3bc2b4c6fa92cd99c5c30
1635%7C0%7C0%7C637012015426788575&sdata=3bx1bDFIzik8FnD0wl
duAUv7wtLdD1J3hQ3xNH2xmFY%3D&reserved=0

and make your patches compliant please.

On Fri, Jun 28, 2019 at 09:38:25AM +0800, Xiaowei Bao wrote:

quoted

The PCIe controller of layerscape just have 4 BARs, BAR0 and BAR1 is
32bit, BAR3 and BAR4 is 64bit, this is determined by hardware, so set
the bar_fixed_64bit with 0x14.

Signed-off-by: Xiaowei Bao <redacted>
---
v2:
 - Replace value 0x14 with a macro.
v3:
 - No change.

 drivers/pci/controller/dwc/pci-layerscape-ep.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c

b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index be61d96..227c33b 100644

--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c

@@ -44,6 +44,7 @@ static int ls_pcie_establish_link(struct dw_pcie *pci)
      .linkup_notifier = false,
      .msi_capable = true,
      .msix_capable = false,
+     .bar_fixed_64bit = (1 << BAR_2) | (1 << BAR_4),

I would appreciate Kishon's ACK on this.

Lorenzo

quoted

 };

 static const struct pci_epc_features*
--
1.7.1