Re: [PATCH v9 0/3] powerpc: Detection and scheduler optimization for POWER9 bigcore

On 10/01/2018 06:16 AM, Gautham R. Shenoy wrote:

Patch 3: Creates a pair of sysfs attributes named
	  /sys/devices/system/cpu/cpuN/topology/smallcore_thread_siblings
	  and
	  /sys/devices/system/cpu/cpuN/topology/smallcore_thread_siblings_list
	  exposing the small-core siblings that share the L1 cache
	  to the userspace.

I really don't think you've justified the existence of a new user/kernel
interface here.  We already have information about threads share L1
caches in here:

	/sys/devices/system/cpu/cpu0/cache/index0/shared_cpu_list

The only question would be if anything would break because it assumes
that all SMT siblings share all caches.  But, it breaks if your new
interface is there or not; it's old software that we care about.