Re: MPC83xx reset status register (RSR, offset 0x910)

Hi,

On Fri, 2018-08-24 at 16:20 +0000, Christophe Leroy wrote:

quoted

On 08/03/2018 04:36 PM, Radu Rendec wrote:

Is there any kernel code that handles the "reset status register" (RSR)
on MPC83xx? I looked at arch/powerpc/platforms/83xx/misc.c, but it seems
to only map the reset register area and it's static. The watchdog driver
(drivers/watchdog/mpc8xxx_wdt.c) doesn't seem to look at it either (for
the bootstatus flags).

How do you boot your Linux kernel ?

My 832x board boots using U-boot, and U-boot reads the RSR then clears
it. So when Linux kernel reads it, it is just 0.

I'm using U-boot as well, but it's just not configured to read or clear
the RSR. I'm curious: if U-boot reads/clears the RSR in your case, how 
do you make the initial value available to user space programs running 
under Linux?

quoted

Basically I need to check the CPU reset reason and I thought I would ask
first, before starting to write any code of my own.

Anyway, find below a set of two patches I used for testing. Feel free to
use them if you bootloader doesn't clear the register

Thank you very much for the patches. Is there any chance they can be 
submitted upstream?

Of course, just printing the decoded bits is only helpful for testing. I
was thinking of a way to make the value available to both the kernel 
(as an exported symbol) and user space (e.g. via sysfs). Is there a
standard or preferred way to do this?

I tried to look for something similar on other platforms or architectures,
but couldn't find anything.

Thanks,
Radu Rendec