Re: [PATCH 2/2] powerpc/64s/radix: Explicitly flush ERAT with local LPID invalidation

On Mon, 27 Aug 2018 18:16:05 +1000
Benjamin Herrenschmidt [off-list ref] wrote:

On Mon, 2018-08-27 at 13:03 +1000, Nicholas Piggin wrote:

quoted

Local radix TLB flush operations that operate on congruence classes
have explicit ERAT flushes for POWER9. The process scoped LPID flush
did not have a flush, so add it. =20

=20
Paul, is that an actual bug ? I think the ERAT is flushed on LPID
changes...

We also have a PPC_INVALIDATE_ERAT in tlbiel_lpid. I'd like to add some
comments for these things because I'm not entirely clear on them myself.

The P9 UM says, "Additionally, mtpidr and mtlpidr instructions perform
an implicit slbia with IH =3D x=E2=80=983=E2=80=99."

Although slbia IH=3D3 does not appear to invalidate LPID!=3D0 && PID=3D=3D0
entries (guest OS mappigs).

The UM also says that tlbiels will clear the involved ERATs, but this
might not match hardware?

Thanks,
Nick

=20

quoted

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/mm/tlb-radix.c | 1 +
 1 file changed, 1 insertion(+)
=20

diff --git a/arch/powerpc/mm/tlb-radix.c b/arch/powerpc/mm/tlb-radix.c
index fef3e1eb3a19..4e798f33c530 100644
--- a/arch/powerpc/mm/tlb-radix.c
+++ b/arch/powerpc/mm/tlb-radix.c

@@ -366,6 +366,7 @@ static inline void _tlbiel_lpid_guest(unsigned long=

 lpid, unsigned long ric)

quoted

 		__tlbiel_lpid_guest(lpid, set, RIC_FLUSH_TLB);
=20
 	asm volatile("ptesync": : :"memory");
+	asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
 }
=20
  =20

=20