Re: [1/2] powernv/npu: Do a PID GPU TLB flush when invalidating a large address range
From: Michael Ellerman <hidden>
Date: 2018-04-24 03:48:27
On Tue, 2018-04-17 at 09:11:28 UTC, Alistair Popple wrote:
The NPU has a limited number of address translation shootdown (ATSD) registers and the GPU has limited bandwidth to process ATSDs. This can result in contention of ATSD registers leading to soft lockups on some threads, particularly when invalidating a large address range in pnv_npu2_mn_invalidate_range(). At some threshold it becomes more efficient to flush the entire GPU TLB for the given MM context (PID) than individually flushing each address in the range. This patch will result in ranges greater than 2MB being converted from 32+ ATSDs into a single ATSD which will flush the TLB for the given PID on each GPU. Signed-off-by: Alistair Popple <redacted> Acked-by: Balbir Singh <bsingharora@gmail.com> Tested-by: Balbir Singh <bsingharora@gmail.com>
Patch 1 applied to powerpc fixes, thanks. https://git.kernel.org/powerpc/c/d0cf9b561ca97d5245bb9e0c4774b7 cheers