Re: [PATCH V4 1/3] powerpc/mm: Add support for handling > 512TB address in SLB miss

diff --git a/arch/powerpc/include/asm/book3s/64/hash-4k.h b/arch/powerpc/=

index 67c5475311ee..af2ba9875f18 100644

--- a/arch/powerpc/include/asm/book3s/64/hash-4k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-4k.h

@@ -11,6 +11,12 @@
 #define H_PUD_INDEX_SIZE  9
 #define H_PGD_INDEX_SIZE  9

=20=20
+/*
+ * No of address bits below which we use the default context

+ * for slb allocation. For 4k this is 64TB.
+ */
+#define H_BITS_FIRST_CONTEXT	46

diff --git a/arch/powerpc/include/asm/book3s/64/hash-64k.h b/arch/powerpc=

index 3bcf269f8f55..0ee0fc1ad675 100644

--- a/arch/powerpc/include/asm/book3s/64/hash-64k.h
+++ b/arch/powerpc/include/asm/book3s/64/hash-64k.h

@@ -6,6 +6,11 @@
 #define H_PMD_INDEX_SIZE  10
 #define H_PUD_INDEX_SIZE  7
 #define H_PGD_INDEX_SIZE  8

+/*
+ * No of address bits below which we use the default context
+ * for slb allocation. For 64k this is 512TB.
+ */
+#define H_BITS_FIRST_CONTEXT	49

diff --git a/arch/powerpc/include/asm/book3s/64/mmu-hash.h b/arch/powerpc=

index 50ed64fba4ae..8ee83f6e9c84 100644

--- a/arch/powerpc/include/asm/book3s/64/mmu-hash.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu-hash.h

@@ -691,8 +691,8 @@ static inline int user_segment_size(unsigned long add=

diff --git a/arch/powerpc/include/asm/book3s/64/mmu.h b/arch/powerpc/incl=

index 777778579305..a70adbb7ec56 100644

--- a/arch/powerpc/include/asm/book3s/64/mmu.h
+++ b/arch/powerpc/include/asm/book3s/64/mmu.h

@@ -91,7 +91,15 @@ struct slice_mask {
 };

=20=20
 typedef struct {
-	mm_context_id_t id;
+	union {
+		/*
+		 * One context for each 512TB.
+		 * First 512TB context is saved in id and is also used
+		 * as PIDR.
+		 */

+	};
 	u16 user_psize;		/* page size index */
=20=20
 	/* Number of bits in the mm_cpumask */

@@ -193,5 +201,21 @@ extern void radix_init_pseries(void);
 static inline void radix_init_pseries(void) { };
 #endif

=20=20
+static inline int get_esid_context(mm_context_t *ctx, unsigned long ea)
+{
+	int index =3D ea >> H_BITS_FIRST_CONTEXT;

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/=

index 01299cdc9806..70d65b482504 100644

--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h

@@ -119,9 +119,16 @@ void release_thread(struct task_struct *);
  */
 #define TASK_SIZE_USER64		TASK_SIZE_512TB
 #define DEFAULT_MAP_WINDOW_USER64	TASK_SIZE_128TB
+#define TASK_CONTEXT_SIZE		TASK_SIZE_512TB
 #else
 #define TASK_SIZE_USER64		TASK_SIZE_64TB
 #define DEFAULT_MAP_WINDOW_USER64	TASK_SIZE_64TB
+/*
+ * We don't need allocate extended context id for 4K
+ * page size. We limit max address on this config to
+ * 64TB.
+ */

diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/e=

index 3ac87e53b3da..166b8c0f1830 100644

--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S

@@ -620,8 +620,12 @@ END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
 	ld	r10,PACA_EXSLB+EX_LR(r13)
 	lwz	r9,PACA_EXSLB+EX_CCR(r13)	/* get saved CR */
 	mtlr	r10

+	/*
+	 * Large address, check whether we have to allocate new
+	 * contexts.
+	 */

@@ -710,7 +714,7 @@ EXC_COMMON_BEGIN(bad_addr_slb)
 	std	r10, _TRAP(r1)
 2:	bl	save_nvgprs
 	addi	r3, r1, STACK_FRAME_OVERHEAD
-	bl	slb_miss_bad_addr

diff --git a/arch/powerpc/mm/mmu_context_book3s64.c b/arch/powerpc/mm/mmu=

index 80acad52b006..ccc88fa7c35c 100644

--- a/arch/powerpc/mm/mmu_context_book3s64.c
+++ b/arch/powerpc/mm/mmu_context_book3s64.c

@@ -178,6 +178,19 @@ void __destroy_context(int context_id)
 }
 EXPORT_SYMBOL_GPL(__destroy_context);

=20=20
+static void destroy_contexts(mm_context_t *ctx)
+{
+	int index, context_id;
+
+	spin_lock(&mmu_context_lock);
+	for (index =3D 0; index < (TASK_SIZE_USER64/TASK_CONTEXT_SIZE); index++=

diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index 13cfe413b40d..a93887ee9b22 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c

@@ -23,6 +23,7 @@
 #include <asm/smp.h>
 #include <linux/compiler.h>
 #include <linux/mm_types.h>
+#include <linux/context_tracking.h>

@@ -340,3 +341,156 @@ void slb_initialize(void)

=20=20
 	asm volatile("isync":::"memory");
 }
+
+/*
+ * Only handle insert of 1TB slb entries.

+ */
+static void insert_slb_entry(unsigned long vsid, unsigned long ea,
+			     int bpsize, int ssize)

+{
+	int slb_cache_index;
+	unsigned long flags;
+	enum slb_index index;
+	unsigned long vsid_data, esid_data;

+
+	/*
+	 * We are irq disabled, hence should be safe
+	 * to access PACA.

+	 */
+	if (index < mmu_slb_size)
+		index++;
+	else
+		index =3D SLB_NUM_BOLTED;

+	get_paca()->stab_rr =3D index;
+
+	flags =3D SLB_VSID_USER | mmu_psize_defs[bpsize].sllp;
+	vsid_data =3D  (vsid << SLB_VSID_SHIFT_1T) | flags |
+		((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);

+	esid_data =3D mk_esid_data(ea, mmu_highuser_ssize, index);
+
+	asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data)
+		     : "memory");

+	/*
+	 * Now update slb cache entries
+	 */
+	slb_cache_index =3D get_paca()->slb_cache_ptr;
+	if (slb_cache_index < SLB_CACHE_ENTRIES) {
+		/*
+		 * We have space in slb cache for optimized switch_slb().
+		 * Top 36 bits from esid_data as per ISA
+		 */
+		get_paca()->slb_cache[slb_cache_index++] =3D esid_data >> 28;
+	}

+	/*
+	 * if we are full, just increment and return.
+	 */
+	get_paca()->slb_cache_ptr++;
+}
+
+static void alloc_extended_context(struct mm_struct *mm, unsigned long e=

+{
+	int context_id;
+
+	int index =3D ea >> H_BITS_FIRST_CONTEXT;
+
+	/*
+	 * we need to do locking only here. If this value was not set before
+	 * we will have taken an SLB miss and will reach here. The value will
+	 * be either 0 or a valid extended context. We need to make sure two
+	 * parallel SLB miss don't end up allocating extended_context for the
+	 * same range. The locking below ensures that. For now we take the
+	 * heavy mmap_sem. But can be changed to per mm_context_t custom lock
+	 * if needed.
+	 */
+	down_read(&mm->mmap_sem);

+	context_id =3D hash__alloc_context_id();
+	if (context_id < 0) {
+		up_read(&mm->mmap_sem);
+		pagefault_out_of_memory();
+		return;
+	}

+	/* Check for parallel allocation after holding lock */
+	if (!mm->context.extended_id[index])
+		mm->context.extended_id[index] =3D context_id;
+	else
+		__destroy_context(context_id);

+	up_read(&mm->mmap_sem);
+}
+
+static void __handle_multi_context_slb_miss(struct pt_regs *regs,
+					    unsigned long ea)
+{
+	int context, bpsize;
+	unsigned long vsid;
+	struct mm_struct *mm =3D current->mm;
+
+	context =3D get_esid_context(&mm->context, ea);
+	if (!context) {
+		/*
+		 * haven't allocated context yet for this range.
+		 * Enable irq and allo context and return. We will
+		 * take an slb miss on this again and come here with
+		 * allocated context.
+		 */
+		/* We restore the interrupt state now */
+		if (!arch_irq_disabled_regs(regs))
+			local_irq_enable();
+		return alloc_extended_context(mm, ea);

+	}
+	/*
+	 * We are always above 1TB, hence use high user segment size.
+	 */
+	vsid =3D __get_vsid(context, ea, mmu_highuser_ssize);
+	bpsize =3D get_slice_psize(mm, ea);
+
+	insert_slb_entry(vsid, ea, bpsize, mmu_highuser_ssize);
+}
+
+/*
+ * exception_enter() handling? FIXME!!

+{
+	enum ctx_state prev_state =3D exception_enter();
+	unsigned long ea =3D regs->dar;
+
+	/*
+	 * Kernel always runs with single context. Hence
+	 * anything that request for multi context is
+	 * considered bad slb request.
+	 */
+	if (!user_mode(regs))
+		return bad_page_fault(regs, ea, SIGSEGV);

+	 */
+	if ((ea & ~REGION_MASK) >=3D H_PGTABLE_RANGE)
+		goto slb_bad_addr;
+
+#ifdef CONFIG_PPC_MM_SLICES

+	/*
+	 * consider this as bad slb if we take an slb miss
+	 * on an address above addr limit.

+	 */
+	if (ea >=3D current->mm->context.slb_addr_limit)
+		goto slb_bad_addr;
+#endif

+	if (ea < (1UL << H_BITS_FIRST_CONTEXT))
+		goto slb_bad_addr;
+
+	__handle_multi_context_slb_miss(regs, ea);
+	exception_exit(prev_state);
+	return;
+
+slb_bad_addr:
+	_exception(SIGSEGV, regs, SEGV_BNDERR, ea);
+	exception_exit(prev_state);
+}

diff --git a/arch/powerpc/mm/slb_low.S b/arch/powerpc/mm/slb_low.S
index 2c7c717fd2ea..c66cb06e73a1 100644
--- a/arch/powerpc/mm/slb_low.S
+++ b/arch/powerpc/mm/slb_low.S

@@ -75,10 +75,12 @@ ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_68_BIT_VA)
  */
 _GLOBAL(slb_allocate)
 	/*
-	 * check for bad kernel/user address
+	 * Check for address range for which we need to handle multi context. F=