[PATCH v2 02/30] powerpc: add TEXASR related macros
flat view
STALE3090d
SUPERSEDED: 1 (0M)
From: <hidden>
Date: 2018-02-27 17:38:23
Also in:
kvm
Subsystem:
linux for powerpc (32-bit and 64-bit), the rest · Maintainers:
Madhavan Srinivasan, Linus Torvalds
Status: Superseded by v4 (posted 2018-05-23). [go to v4]
Revision v2 (4 revisions archived); 1 review trailer.
Revisions (4)
From: Simon Guo <redacted>
This patches add some macros for CR0/TEXASR bits so that PR KVM TM
logic(tbegin./treclaim./tabort.) can make use of them later.
Signed-off-by: Simon Guo <redacted>
Reviewed-by: Paul Mackerras <redacted>
---
arch/powerpc/include/asm/reg.h | 25 ++++++++++++++++++++++++-
arch/powerpc/platforms/powernv/copy-paste.h | 3 +--
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 14e41b8..173c857 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h@@ -146,6 +146,12 @@ #define MSR_64BIT 0 #endif +/* Condition Register related */ +#define CR0_SHIFT 28 +#define CR0_MASK 0xF +#define CR0_TBEGIN_FAILURE (0x2 << 28) /* 0b0010 */ + + /* Power Management - Processor Stop Status and Control Register Fields */ #define PSSCR_RL_MASK 0x0000000F /* Requested Level */ #define PSSCR_MTL_MASK 0x000000F0 /* Maximum Transition Level */
@@ -237,8 +243,25 @@ #define SPRN_TFIAR 0x81 /* Transaction Failure Inst Addr */ #define SPRN_TEXASR 0x82 /* Transaction EXception & Summary */ #define SPRN_TEXASRU 0x83 /* '' '' '' Upper 32 */ -#define TEXASR_FS __MASK(63-36) /* TEXASR Failure Summary */ +#define TEXASR_FC_LG (63 - 7) /* Failure Code */ +#define TEXASR_AB_LG (63 - 31) /* Abort */ +#define TEXASR_SU_LG (63 - 32) /* Suspend */ +#define TEXASR_HV_LG (63 - 34) /* Hypervisor state*/ +#define TEXASR_PR_LG (63 - 35) /* Privilege level */ +#define TEXASR_FS_LG (63 - 36) /* failure summary */ +#define TEXASR_EX_LG (63 - 37) /* TFIAR exact bit */ +#define TEXASR_ROT_LG (63 - 38) /* ROT bit */ +#define TEXASR_FC (ASM_CONST(0xFF) << TEXASR_FC_LG) +#define TEXASR_AB __MASK(TEXASR_AB_LG) +#define TEXASR_SU __MASK(TEXASR_SU_LG) +#define TEXASR_HV __MASK(TEXASR_HV_LG) +#define TEXASR_PR __MASK(TEXASR_PR_LG) +#define TEXASR_FS __MASK(TEXASR_FS_LG) +#define TEXASR_EX __MASK(TEXASR_EX_LG) +#define TEXASR_ROT __MASK(TEXASR_ROT_LG) + #define SPRN_TFHAR 0x80 /* Transaction Failure Handler Addr */ + #define SPRN_TIDR 144 /* Thread ID register */ #define SPRN_CTRLF 0x088 #define SPRN_CTRLT 0x098
diff --git a/arch/powerpc/platforms/powernv/copy-paste.h b/arch/powerpc/platforms/powernv/copy-paste.h
index c9a5036..3fa62de 100644
--- a/arch/powerpc/platforms/powernv/copy-paste.h
+++ b/arch/powerpc/platforms/powernv/copy-paste.h@@ -7,9 +7,8 @@ * 2 of the License, or (at your option) any later version. */ #include <asm/ppc-opcode.h> +#include <asm/reg.h> -#define CR0_SHIFT 28 -#define CR0_MASK 0xF /* * Copy/paste instructions: *
--
1.8.3.1