Re: [PATCH RFC 0/7] powerpc: Beef up single-stepping/instruction emulation infrastructure

Paulus,=20

This patch series extends the code in arch/powerpc/lib/sstep.c so that
it handles almost all load and store instructions -- all except the
atomic memory operations (lwat, stwat, etc.).=C2=A0=C2=A0It also makes su=

re that

we use the largest possible aligned accesses to access memory and that
we don't access the CPU FP/VMX/VSX registers when they don't contain
user data.

Do you have any test cases we can put in selftests for this?

With this, it should be possible to replace the body of the alignment
interrupt handler with a call to emulate_step() or something quite
similar.

Exercise for the reader? :-)

Mikey