[PATCH 2/3] powerpc/pseries/le: work around a firmware quirk
From: Nicholas Piggin <npiggin@gmail.com>
Date: 2017-07-04 10:09:36
Subsystem:
linux for powerpc (32-bit and 64-bit), the rest · Maintainers:
Madhavan Srinivasan, Linus Torvalds
Some PowerVM firmware when delivering a system reset interrupt to a little endian OS will mess up SRR registers. They are byteswapped, and SRR1 is incorrect. An example from a crash: NIP: 14dd0900000000c0 MSR: 1000000200000080 It's possible to detect this pattern in SRR1 (that would never happen in normal operation), and at least fix the NIP. After this patch, the same interrupt reports NIP properly: NIP [c00000000009dd14] plpar_hcall_norets+0x1c/0x28 Signed-off-by: Nicholas Piggin <npiggin@gmail.com> --- arch/powerpc/platforms/pseries/ras.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/powerpc/platforms/pseries/ras.c b/arch/powerpc/platforms/pseries/ras.c
index bb70b26334f0..4923ffe230cf 100644
--- a/arch/powerpc/platforms/pseries/ras.c
+++ b/arch/powerpc/platforms/pseries/ras.c@@ -379,6 +379,21 @@ static void fwnmi_release_errinfo(void) int pSeries_system_reset_exception(struct pt_regs *regs) { +#ifdef __LITTLE_ENDIAN__ + /* + * Some firmware byteswaps SRR registers and gives incorrect SRR1. Try + * to detect the bad SRR1 pattern here. Flip the NIP back to correct + * endian for reporting purposes. Unfortunately the MSR can't be fixed, + * so clear it. It will be missing MSR_RI so we won't try to recover. + */ + if ((be64_to_cpu(regs->msr) & + (MSR_LE|MSR_RI|MSR_DR|MSR_IR|MSR_ME|MSR_PR| + MSR_ILE|MSR_HV|MSR_SF)) == (MSR_DR|MSR_SF)) { + regs->nip = be64_to_cpu((__be64)regs->nip); + regs->msr = 0; + } +#endif + if (fwnmi_active) { struct rtas_error_log *errhdr = fwnmi_get_errinfo(regs); if (errhdr) {
--
2.11.0