Re: [PATCH 12/13] powerpc/64: runlatch CTRL[RUN] set optimisation

Nicholas Piggin [off-list ref] writes:

The CTRL register is read-only except bit 63 which is the run latch
control. This means it can be updated with a mtspr rather than
mfspr/mtspr.

Turns out this doesn't work on Cell.

There's an extra field in there:

  Thread enable bits (Read/Write)
  The hypervisor state can suspend its own thread by setting the TE bit
  for its thread to '0=E2=80=99. The hypervisor state can resume the opposi=
te
  thread by setting the TE bit for the opposite thread to '1'. The
  hypervisor state cannot suspend the opposite thread by setting the TE
  bit for the opposite thread to =E2=80=980=E2=80=99. This setting is ignor=
ed and does not
  cause an error.
=20=20
  TE0 is the thread enable bit for thread 0.
  TE1 is the thread enable bit for thread 1.
=20=20
  If thread 0 executes the mtctrl instruction, these are the bit values:
=20=20
  [TE0 TE1] Description
    0   0   Disable or suspend thread 0; thread 1 unchanged.
    0   1   Disable or suspend thread 0; enable or resume thread 1 if it wa=
s disabled.
    1   0   Unchanged.
    1   1   Enable or resume thread 1 if it was disabled.
=20=20
  If thread 1 executes the mtctrl instruction, these are the bit values:
=20=20
  [TE0 TE1] Description
    0   0    Thread 0 unchanged; disable or suspend thread 1.
    0   1    Unchanged.
    1   0    Enable or resume thread 0 if it was disabled; disable or suspe=
nd thread 1.
    1   1    Enable or resume thread 0 if it was disabled.


So writing either 0 or CTRL_RUNLATCH (1) will disable the thread that
does the write - :D

For now I'll just drop this.

cheers