[bug report] [POWERPC] 4xx: Add 405GPr and 405EP support in boot wrapper

Hello Matthias Fuchs,

The patch 2af59f7d5c3e: "[POWERPC] 4xx: Add 405GPr and 405EP support
in boot wrapper" from Dec 7, 2007, leads to the following static
checker warning:

	arch/powerpc/boot/4xx.c:567 ibm405gp_fixup_clocks()
	warn: mask and shift to zero

arch/powerpc/boot/4xx.c
   552  void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
   553  {
   554          u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
   555          u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
   556          u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
   557          u32 psr = mfdcr(DCRN_405_CPC0_PSR);
   558          u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
   559          u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
   560  
   561          fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
   562          fbdv = (pllmr & 0x1e000000) >> 25;
   563          if (fbdv == 0)
   564                  fbdv = 16;
   565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
   566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
   567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
                                 ^^^^^^^^^^^^^^^^^
This is zero.  It looks like 0x00000600 was probably intended?

   568          epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
   569          udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
   570  
   571          /* check for 405GPr */

regards,
dan carpenter

On Wed, 2016-10-26 at 16:03 +0300, Dan Carpenter wrote:

   565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
   566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
   567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
                                 ^^^^^^^^^^^^^^^^^
This is zero.  It looks like 0x00000600 was probably intended?

I just checked the spec and for the 405gp and it's 0x6000 (bits 17 and
18 in IBM ordering)

Cheers,
Ben.

On Wed, Oct 26, 2016 at 01:57:23PM -0500, Benjamin Herrenschmidt wrote:

On Wed, 2016-10-26 at 16:03 +0300, Dan Carpenter wrote:

quoted

   565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
   566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
   567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
                                 ^^^^^^^^^^^^^^^^^
This is zero.  It looks like 0x00000600 was probably intended?

I just checked the spec and for the 405gp and it's 0x6000 (bits 17 and
18 in IBM ordering)

I'm on the road and there is no way I'm going to remember to do this
when I get back...  Could you send the patch?

regards,
dan carpenter

On Wed, 2016-10-26 at 22:07 +0300, Dan Carpenter wrote:

On Wed, Oct 26, 2016 at 01:57:23PM -0500, Benjamin Herrenschmidt
wrote:

quoted

On Wed, 2016-10-26 at 16:03 +0300, Dan Carpenter wrote:

quoted

   565          cbdv = ((pllmr & 0x00060000) >> 17) + 1; /*
CPU:PLB */
   566          opdv = ((pllmr & 0x00018000) >> 15) + 1; /*
PLB:OPB */
   567          ppdv = ((pllmr & 0x00001800) >> 13) + 1; /*
PLB:PCI */
                                 ^^^^^^^^^^^^^^^^^
This is zero.  It looks like 0x00000600 was probably intended?

I just checked the spec and for the 405gp and it's 0x6000 (bits 17
and
18 in IBM ordering)

I'm on the road and there is no way I'm going to remember to do this
when I get back...  Could you send the patch?

I'll try to remember when I'm out of meeting frenzy ;-)

Cheers,
Ben.