Thread (8 messages) 8 messages, 4 authors, 2016-10-13

Re: [PATCH 2/2] powernv: Pass PSSCR value and mask to power9_idle_stop

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From: Gautham R Shenoy <hidden>
Date: 2016-10-07 07:21:11
Also in: linux-pm, lkml

Hi Balbir, Michael,

On Tue, Oct 04, 2016 at 10:33:27PM +1100, Balbir Singh wrote:

On 04/10/16 21:32, Michael Ellerman wrote:
quoted
"Gautham R. Shenoy" [off-list ref] writes:
quoted
From: "Gautham R. Shenoy" <redacted>

The power9_idle_stop method currently takes only the requested stop
level as a parameter and picks up the rest of the PSSCR bits from a
hand-coded macro. This is not a very flexible design, especially when
the firmware has the capability to communicate the psscr value and the
mask associated with a particular stop state via device tree.

This patch modifies the power9_idle_stop API to take as parameters the
PSSCR value and the PSSCR mask corresponding to the stop state that
needs to be set. These PSSCR value and mask are respectively obtained
by parsing the "ibm,cpu-idle-state-psscr" and
"ibm,cpu-idle-state-psscr-mask" fields from the device tree.

In addition to this, the patch adds support for handling stop states
for which ESL and EC bits in the PSSCR are zero. As per the
architecture, a wakeup from these stop states resumes execution from
the subsequent instruction as opposed to waking up at the System
Vector.
That looks good.
quoted
This patch depends on the following skiboot patch that exports the
PSSCR values and the mask for all the stop states:
https://lists.ozlabs.org/pipermail/skiboot/2016-September/004869.html
But we can't depend on a skiboot patch. The kernel has to cope with
running on an old skiboot.
Hmm.. We can still do that. The older skiboot only provides the RL
field of the PSSCR value for each stop state and the corresponding
PSSCR mask is set to 0xF in the older skiboot for all the stop states.

We can insist that the future skiboot sets the ESL, EC, PSLL, TR, MTL
and the the RL fields of the PSSCR for any exported stop state. This
should be reflected in the psscr_mask of that stop state.  Thus, the
psscr_mask of any stop state proposed in the future will have:
(PSSCR_ESL_MASK | PSCCR_EC_MASK | PSCCR_PSLL_MASK | PSSCR_TR_MASK |
PSSCR_MTL_MASK | PSSCR_RL_MASK) bits set in the skiboot.

To handle the older firmware, we can do something like the following
during the discovery of the stop states to mimic the behaviour present
in the 4.8 kernel running on older firmware.

=============== drivers/cpuidle/cpuidle-powernv.c =======================
/*
 * By default we set the ESL and EC bits in the PSSCR.
 * The MTL and PSLL are set to the maximum value possible as per the
 * ISA, i.e 15.
 * The Transition Rate is set to the Maximum value 3.
 */
#define DEFAULT_PSSCR_VAL      PSSCR_ESL_MASK |			\
			       PSCCR_EC_MASK | PSCCR_PSLL_MASK |\
			       PSSCR_TR_MASK | PSSCR_MTL_MASK

#define DEFAULT_PSSCR_MASK     PSSCR_ESL_MASK |			\
			       PSCCR_EC_MASK | PSCCR_PSLL_MASK |\
			       PSSCR_TR_MASK | PSSCR_MTL_MASK | \
			       PSSCR_RL_MASK


static int powernv_add_idle_states(void)
{
	.
	.
	.
	for (i = 0; i < dt_idle_states; i++) {
	    u64 val, mask;
	    	.	    
		.
		.
		val = (DEFAULT_PSSCR_VAL & ~psscr_mask[i]) | psscr_val[i];
		mask = DEFAULT_PSSCR_MASK | psscr_mask[i];
		stop_psscr_table[nr_idle_states].val = val;
        	stop_psscr_table[nr_idle_states].mask = mask;
	}
}		
============================================================================


Is this approach ok ?

Hi, Michael

I think with an older skiboot the flags don't get exported and the
new cpuidle (stop state) does not get discovered. I don't think there
is any breakage. Gautham am I missing something?
In the second verison of the patch, I am not adding any new flags in
the skiboot, but explicitly providing the psscr_value and psscr_mask
for each stop state.  Thus if you see the v2 of the skiboot patch, the
lite versions of stop0,stop1 and stop2 are defined with no additional
flags.

The second version of the kernel patch wouldn't then work with the
older skiboot since the older skiboot exports only the RL field of the
psscr_val while the new kernel patch expects all the relavant bits of
the psscr_val be set. This would result in a breakage.

Balbir Singh.
--
Thanks and Regards
gautham.
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