Re: [PATCH v3 7/9] powerpc/powernv: Add platform support for stop instruction

On 05/24/2016 02:17 PM, Madhavan Srinivasan wrote:

On Monday 23 May 2016 08:48 PM, Shreyas B. Prabhu wrote:

quoted

POWER ISA v3 defines a new idle processor core mechanism. In summary,
 a) new instruction named stop is added. This instruction replaces
	instructions like nap, sleep, rvwinkle.
 b) new per thread SPR named PSSCR is added which controls the behavior
	of stop instruction.

Kindly expand the register name at first use like
Processor Stop Status and Control Register (PSSCR)

quoted

PSSCR has following key fields

Having the PSSCR layout here will help? something like this

----------------------------------------------------------
| PLS | /// | SD | ESL | EC | PSLL | /// | TR | MTL | RL |
----------------------------------------------------------
0      4     41   42    43   44     48    54   56    60  

quoted

	Bits 0:3  - Power-Saving Level Status. This field indicates the lowest
	power-saving state the thread entered since stop instruction was last
	executed.

	Bit 42 - Enable State Loss
	0 - No state is lost irrespective of other fields
	1 - Allows state loss

	Bits 44:47 - Power-Saving Level Limit
	This limits the power-saving level that can be entered into.

	Bits 60:63 - Requested Level
	Used to specify which power-saving level must be entered on executing
	stop instruction

This patch adds support for stop instruction and PSSCR handling.

Signed-off-by: Shreyas B. Prabhu <redacted>
---

Hi Madhavan,

Thanks for the review. I have incorporated your review comments in v4.


Thanks,
Shreyas