On 10/05/16 14:57, Oliver O'Halloran wrote:

POWER ISA v3 adds large decrementer (LD) mode of operation which increases
the size of the decrementer register from 32 bits to an implementation
defined with of up to 64 bits.

This patch adds support for the LD on processors with the CPU_FTR_ARCH_300
cpu feature flag set. For CPUs with this feature LD mode is enabled when
when the ibm,dec-bits devicetree property is supplied for the boot CPU. The
decrementer value is a signed quantity (with negative values indicating a
pending exception) and this property is required to find the maximum
positive decrementer value. If this property is not supplied then the
traditional decrementer width of 32 bits is assumed and LD mode is disabled.

This patch was based on initial work by Jack Miller.

Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Cc: Michael Neuling <redacted>
Cc: Balbir Singh <bsingharora@gmail.com>
Cc: Jack Miller <redacted>

These bits look good mostly

Reviewed-by: Balbir Singh <bsingharora@gmail.com>