On Sun, 2016-05-08 at 13:44 +0200, Christian Lamparter wrote:
On Sunday, May 08, 2016 08:40:55 PM Benjamin Herrenschmidt wrote:
quoted
On Sun, 2016-05-08 at 00:54 +0200, Christian Lamparter via Linuxppc-dev
wrote:
quoted
I've been looking in getting the MyBook Live Duo's USB OTG port
to function. The SoC is a APM82181. Which has a PowerPC 464 core
and related to the supported canyonlands architecture in
arch/powerpc/.
Currently in -next the dwc2 module doesn't load:
Smells like the APM implementation is little endian. You might need to
use a flag to indicate what endian to use instead and set it
appropriately based on some DT properties.
I tried. As per common-properties[0], I added little-endian; but it has no
effect. I looked in dwc2_driver_probe and found no way of specifying the
endian of the device. It all comes down to the dwc2_readl & dwc2_writel
accessors. These - sadly - have been hardwired to use __raw_readl and
__raw_writel. So, it's always "native-endian". While common-properties
says little-endian should be preferred.
Right, I meant, you should produce a patch adding a runtime test inside
those functions based on a device-tree property, a bit like we do for
some of the HCDs like OHCI, EHCI etc...
Cheers,
Ben.
quoted
quoted
dwc2 4bff80000.usbotg: dwc2_core_reset() HANG! AHB Idle GRSTCTL=80
dwc2 4bff80000.usbotg: Bad value for GSNPSID: 0x0a29544f
Looking at the Bad GSNPSID value: 0x0a29544f. It is obvious that
this is an endian problem. git finds this patch:
commit 95c8bc3609440af5e4a4f760b8680caea7424396
Author: Antti Seppälä [off-list ref]
Date: Thu Aug 20 21:41:07 2015 +0300
usb: dwc2: Use platform endianness when accessing registers
This patch is necessary to access dwc2 registers correctly on
big-endian
systems such as the mips based SoCs made by Lantiq. Then dwc2 can
be
used to replace ifx-hcd driver for Lantiq platforms found e.g. in
OpenWrt.
The patch was autogenerated with the following commands:
$EDITOR core.h
sed -i "s/\/dwc2_readl/g" *.c hcd.h hw.h
sed -i "s/\/dwc2_writel/g" *.c hcd.h hw.h
Some files were then hand-edited to fix checkpatch.pl warnings
about
too long lines.
which unfortunately, broke the USB-OTG port on the MyBook Live Duo.
Reverting to the readl / writel:
---
diff --git a/drivers/usb/dwc2/core.h b/drivers/usb/dwc2/core.h
index 3c58d63..c021c1f 100644
--- a/drivers/usb/dwc2/core.h
+++ b/drivers/usb/dwc2/core.h
static inline u32 dwc2_readl(const void __iomem *addr)
{
- u32 value = __raw_readl(addr);
+ u32 value = readl(addr);
/* In order to preserve endianness __raw_* operation is
used. Therefore
* a barrier is needed to ensure IO access is not re-ordered
across@@ -78,7 +78,7 @@ static inline u32 dwc2_readl(const void __iomem
*addr)
static inline void dwc2_writel(u32 value, void __iomem *addr)
{
- __raw_writel(value, addr);
+ writel(value, addr);
/*
* In order to preserve endianness __raw_* operation is
used. Therefore
---
restores the dwc-otg port to full working order:
dwc2 4bff80000.usbotg: Specified GNPTXFDEP=1024 > 256
dwc2 4bff80000.usbotg: EPs: 3, shared fifos, 2042 entries in SPRAM
dwc2 4bff80000.usbotg: DWC OTG Controller
dwc2 4bff80000.usbotg: new USB bus registered, assigned bus number 1
dwc2 4bff80000.usbotg: irq 33, io mem 0x00000000
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
root@mbl:~# usb 1-1: new high-speed USB device number 2 using dwc2
So, what to do?
^^^
Regards,
Christian
[0]
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