[PATCH] cxl: Fix PSL timebase synchronization detection

The PSL timebase synchronization is seemingly failing for
configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
shows the following trace in dmesg:
PSL: Timebase sync: giving up!

The PSL timebase register is actually syncing correctly, but the cxl
driver is not detecting it. Fix is to use the proper timebase-to-time
conversion.

Signed-off-by: Frederic Barrat <redacted>
Cc: <redacted> # 4.3+
---
 drivers/misc/cxl/pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 4c1903f..0c6c17a1 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c

@@ -415,7 +415,7 @@ static int cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
 		delta = mftb() - psl_tb;
 		if (delta < 0)
 			delta = -delta;
-	} while (cputime_to_usecs(delta) > 16);
+	} while (tb_to_ns(delta) > 16000);
 
 	return 0;
 }

-- 
1.9.1

On Wed, 2016-02-24 at 18:27 +0100, Frederic Barrat wrote:

The PSL timebase synchronization is seemingly failing for
configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
shows the following trace in dmesg:
PSL: Timebase sync: giving up!
=20
The PSL timebase register is actually syncing correctly, but the cxl
driver is not detecting it. Fix is to use the proper timebase-to-time
conversion.
=20
Signed-off-by: Frederic Barrat <redacted>

Looks good!

Acked-by: Michael Neuling <redacted>

Reviewed-by: Matthew R. Ochs <redacted>

Acked-by: Ian Munsie <redacted>

On 25/02/16 04:27, Frederic Barrat wrote:

The PSL timebase synchronization is seemingly failing for
configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
shows the following trace in dmesg:
PSL: Timebase sync: giving up!

The PSL timebase register is actually syncing correctly, but the cxl
driver is not detecting it. Fix is to use the proper timebase-to-time
conversion.

Signed-off-by: Frederic Barrat <redacted>
Cc: <redacted> # 4.3+

Reviewed-by: Andrew Donnellan <redacted>


-- 
Andrew Donnellan              Software Engineer, OzLabs
andrew.donnellan@au1.ibm.com  Australia Development Lab, Canberra
+61 2 6201 8874 (work)        IBM Australia Limited

Frederic Barrat [off-list ref] writes:

The PSL timebase synchronization is seemingly failing for
configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
shows the following trace in dmesg:
PSL: Timebase sync: giving up!

The PSL timebase register is actually syncing correctly, but the cxl
driver is not detecting it. Fix is to use the proper timebase-to-time
conversion.

Signed-off-by: Frederic Barrat <redacted>
Cc: <redacted> # 4.3+

Reviewed-by: Vaibhav Jain <redacted>

On Wed, 2016-24-02 at 17:27:51 UTC, Frederic Barrat wrote:

The PSL timebase synchronization is seemingly failing for
configuration not including VIRT_CPU_ACCOUNTING_NATIVE. The driver
shows the following trace in dmesg:
PSL: Timebase sync: giving up!

The PSL timebase register is actually syncing correctly, but the cxl
driver is not detecting it. Fix is to use the proper timebase-to-time
conversion.

Signed-off-by: Frederic Barrat <redacted>
Cc: <redacted> # 4.3+
Acked-by: Michael Neuling <redacted>
Reviewed-by: Matthew R. Ochs <redacted>
Acked-by: Ian Munsie <redacted>
Reviewed-by: Andrew Donnellan <redacted>
Reviewed-by: Vaibhav Jain <redacted>

Applied to powerpc fixes, thanks.

https://git.kernel.org/powerpc/c/923adb1646d5ba739d2a1e63ee

cheers