Re: RFC: Reducing the number of non volatile GPRs in the ppc64 kernel

On Tue, Aug 11, 2015 at 03:08:29PM -0500, Segher Boessenkool wrote:

[snip code]

After the prologue there are 46 insns executed before the epilogue.
Many of those are conditional branches (that are not executed); it is
all fall-through until it jumps to the "tail" (the few insns before
the epilogue).  GCC knows how to duplicate a tail so that it can do
shrink-wrapping (the original tail needs to be followed by an epilogue,
the duplicated one does not want one); but it can only do it in very
simple cases (one basic block or at least no control flow), and that
is not the case here.  We need to handle more generic tails.

And never mind the elephant in the room: the "fastpath" instructions
already use a few non-volatile registers, and the shrink-wrap pass
(which runs after register allocation) cannot fix that.  Ugh.

This seems related to (if not the same as!) <http://gcc.gnu.org/PR51982>.

This has that same problem, too.


Segher