Thread (7 messages) 7 messages, 4 authors, 2015-05-26

Re: [alsa-devel] [PATCH] ASoC: fsl_spdif: Don't try to round-up for clock divisor calculation

From: Zidan Wang <hidden>
Date: 2015-05-26 13:43:24
Also in: alsa-devel, lkml

On Mon, May 25, 2015 at 08:24:25AM -0700, Nicolin Chen wrote:
On Mon, May 25, 2015 at 12:13:45PM -0300, Fabio Estevam wrote:
quoted
Hi Nicolin,

On Mon, May 25, 2015 at 12:11 PM, Nicolin Chen [off-list ref] wrote:
quoted
Hi Mark,

Is that possible for you to provisionally revert this patch?
I wanted to wait for the test result from Fabio or Zidan in
the Cc list because I don't have a test environment for SPDIF
even though this change seems to make sense.
I currently don't have access to a SPDIF receiver to test it.
Okay, let's wait for Zidan then. We only need to test the
playback route of supporting sample rates.

Thanks
Nicolin
I don't have the board which supported by community to test spdif out. So i used the imx7 board
and test it with internal branch.
I found that (txclk_df + 1) is better than txclk_df.
I suspect the patch for clk_round_rate() is not in our branch. Could you please tell me which
patch is for clk_round_rate? I want to cherry-pick it to our branch and test it.

Best Regards,
Zidan Wang
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help