Re: [PATCH 1/4] CXL: Use image state defaults for reloading FPGA

On Mon, 2015-01-19 at 16:03 +1100, Ian Munsie wrote:

Acked-by: Ian Munsie <redacted>

Looks like you forgot your Signed-off-by line - mpe, do you want Ryan to
resend the whole patch (maybe with the below explanation included), or
just reply with a Signed-off-by?

Just resend the series please.

This would also be good to CC: Stable, as these new defaults mean that
the card will be fully reset when sapphire PERSTs them on reboot,
whereas before it was left up to the default value of this register in
each card, and could lead to a card getting into a bad state requiring a
full power cycle to recover. The symptoms we saw was the tlbia / slbia
we do on boot timing out and the driver init aborting.

OK.

I've decided I'm going to handle stable patches differently for the next cycle,
we've been sending too many and then sending fixups and reverts.

So please just note that you'd like it to be considered for stable, under the

--- line, and I'll add it to my list and if it's still good to go in a few

weeks then I'll send it to stable.

cheers