Re: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add CLK_OF_DECLARE support

Quoting Scott Wood (2014-09-25 13:08:00)

Well, like I said, I'd rather see the CLK_OF_DECLARE stuff be made to
work on PPC rather than have the driver carry around two binding
methods.

I guess that is an existing problem, and not related directly to this
patch? This patch is essentially just renames (though the V1.0/V2.0
stuff seems weird).

Regards,
Mike

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-Scott
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On Thu, 2014-09-25 at 04:47 -0500, Lu Jingchang-B35083 wrote:

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Hi, Scott and Mike,
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  Could you please help review this patch and give an ACK if ok. Thanks.
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Best Regards,
Jingchang
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-----Original Message-----
From: Jingchang Lu [mailto:jingchang.lu@freescale.com]
Sent: Tuesday, September 23, 2014 2:47 PM
To: mturquette@linaro.org
Cc: Wood Scott-B07421; linuxppc-dev@lists.ozlabs.org; linux-
kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Lu
Jingchang-B35083
Subject: [PATCHv4] clk: ppc-corenet: rename to ppc-qoriq and add
CLK_OF_DECLARE support

The IP is shared by PPC and ARM, this renames it to qoriq for better
represention, and this also adds the CLK_OF_DECLARE support for being
initialized by of_clk_init() on ARM.

Signed-off-by: Jingchang Lu <redacted>
---
changes in v4:
remove "corenet" literals omitted in v3 remove.

changes in v3:
generate the patch with -M -C option

changes in v2:
rename the driver name to ppc-qoriq.c for shared on PPC and ARM.

drivers/clk/Kconfig                            |  9 +++++----
drivers/clk/Makefile                           |  2 +-
drivers/clk/{clk-ppc-corenet.c =3D> clk-qoriq.c} | 27 +++++++++++++++=

------

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-----
3 files changed, 22 insertions(+), 16 deletions(-)  rename
drivers/clk/{clk-ppc-corenet.c =3D> clk-qoriq.c} (89%)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index

85131ae..f5f76cb 100644

--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig

@@ -92,12 +92,13 @@ config COMMON_CLK_AXI_CLKGEN
      Support for the Analog Devices axi-clkgen pcore clock generator

for Xilinx
      FPGAs. It is commonly used in Analog Devices' reference designs.

-config CLK_PPC_CORENET
-    bool "Clock driver for PowerPC corenet platforms"
-    depends on PPC_E500MC && OF
+config CLK_QORIQ
+    bool "Clock driver for PowerPC corenet and compatible ARM-based
platforms"
+    depends on (PPC_E500MC || ARM) && OF
    ---help---
      This adds the clock driver support for Freescale PowerPC corenet
-      platforms using common clock framework.
+      platforms and compatible Freescale ARM based platforms using
common
+      clock framework.

config COMMON_CLK_XGENE
    bool "Clock driver for APM XGene SoC"

diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index

27c542b..20f42e9 100644

--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile

@@ -29,7 +29,7 @@ obj-$(CONFIG_ARCH_MOXART)          +=3D clk-moxart.o

obj-$(CONFIG_ARCH_NOMADIK)          +=3D clk-nomadik.o
obj-$(CONFIG_ARCH_NSPIRE)           +=3D clk-nspire.o
obj-$(CONFIG_COMMON_CLK_PALMAS)             +=3D clk-palmas.o
-obj-$(CONFIG_CLK_PPC_CORENET)               +=3D clk-ppc-corenet.o
+obj-$(CONFIG_CLK_QORIQ)                     +=3D clk-qoriq.o
obj-$(CONFIG_COMMON_CLK_S2MPS11)    +=3D clk-s2mps11.o
obj-$(CONFIG_COMMON_CLK_SI5351)             +=3D clk-si5351.o
obj-$(CONFIG_COMMON_CLK_SI570)              +=3D clk-si570.o

diff --git a/drivers/clk/clk-ppc-corenet.c b/drivers/clk/clk-qoriq.c
similarity index 89% rename from drivers/clk/clk-ppc-corenet.c rename =

to

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drivers/clk/clk-qoriq.c index 8e58edf..cba8abe 100644

--- a/drivers/clk/clk-ppc-corenet.c
+++ b/drivers/clk/clk-qoriq.c

@@ -155,7 +155,7 @@ static void __init core_pll_init(struct device_node

*np)

    base =3D of_iomap(np, 0);
    if (!base) {
-            pr_err("clk-ppc: iomap error\n");
+            pr_err("clk-qoriq: iomap error\n");
            return;
    }

@@ -252,7 +252,7 @@ static void __init sysclk_init(struct device_node

*node)
    u32 rate;

    if (!np) {
-            pr_err("ppc-clk: could not get parent node\n");
+            pr_err("qoriq-clk: could not get parent node\n");
            return;
    }

@@ -278,30 +278,35 @@ static const struct of_device_id clk_match[]

__initconst =3D {
    {}
};

-static int __init ppc_corenet_clk_probe(struct platform_device *pdev)
+static int __init qoriq_clk_probe(struct platform_device *pdev)
{
    of_clk_init(clk_match);

    return 0;
}

-static const struct of_device_id ppc_clk_ids[] __initconst =3D {
+static const struct of_device_id qoriq_clk_ids[] __initconst =3D {
    { .compatible =3D "fsl,qoriq-clockgen-1.0", },
    { .compatible =3D "fsl,qoriq-clockgen-2.0", },
    {}
};

-static struct platform_driver ppc_corenet_clk_driver __initdata =3D {
+static struct platform_driver qoriq_clk_driver __initdata =3D {
    .driver =3D {
-            .name =3D "ppc_corenet_clock",
+            .name =3D "qoriq_clock",
            .owner =3D THIS_MODULE,
-            .of_match_table =3D ppc_clk_ids,
+            .of_match_table =3D qoriq_clk_ids,
    },
-    .probe =3D ppc_corenet_clk_probe,
+    .probe =3D qoriq_clk_probe,
};

-static int __init ppc_corenet_clk_init(void)
+static int __init qoriq_clk_init(void)
{
-    return platform_driver_register(&ppc_corenet_clk_driver);
+    return platform_driver_register(&qoriq_clk_driver);
}
-subsys_initcall(ppc_corenet_clk_init);
+subsys_initcall(qoriq_clk_init);
+
+CLK_OF_DECLARE(qoriq_core_pll_v1, "fsl,qoriq-core-pll-1.0",
+core_pll_init); CLK_OF_DECLARE(qoriq_core_pll_v2,
+"fsl,qoriq-core-pll-2.0", core_pll_init);
+CLK_OF_DECLARE(qoriq_core_mux_v1, "fsl,qoriq-core-mux-1.0",
+core_mux_init); CLK_OF_DECLARE(qoriq_core_mux_v2,
+"fsl,qoriq-core-mux-2.0", core_mux_init);
--
1.8.0

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