Re: [PATCH v2 5/7] powerpc/corenet: Add MDIO bus muxing support to the board device tree(s)
From: Emil Medve <hidden>
Date: 2014-07-31 05:56:43
Hello Scott, On 07/31/2014 12:28 AM, Scott Wood wrote:
On Wed, 2014-07-30 at 23:35 -0500, Emil Medve wrote:quoted
Hello Scott, On 07/30/2014 09:30 PM, Scott Wood wrote:quoted
On Wed, 2014-07-30 at 16:52 -0500, Emil Medve wrote:quoted
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+ mdio0: mdio <at> fc000 { + };Why is the empty node needed?For the labelFor mdio-parent-bus, or is there some other dts layer that makes this node non-empty?'powerpc/corenet: Create the dts components for the DPAA FMan' - http://patchwork.ozlabs.org/patch/370872Why does this patch define the mdio0 label for mdio@e1120, but not define a label for any other node?Only MDIO controllers that are pinned out have these labels. Only pinned out MDIO(s) are capable of controlling external PHY(s) via these board level MDIO busesIs there any reason to describe non-pinned-out MDIO controllers at all?
Yes. For the internal TBI PHY(s). Each MAC supporting SGMII has a TBI PHY that is attached to the MDIO controller of the respective MAC
Is the lack of pinning out inherent to the silicon, or is it board design/config?
It's a silicon level decision
Is the answer different for different MDIO controllers?
You mean non-FSL MDIO controllers? Dunno. All FSL SoC have the same MDIO pin-out decision
I'm just curious why mdio@e1120 is labelled in a non-board dtsi while others are labelled elsewhere.
Labels are relevant only in the context of 'powerpc/corenet: Add MDIO bus muxing support to the board device tree(s)' - http://patchwork.ozlabs.org/patch/370866. Most labels are created and used in the board .dts file except b4qds.dtsi which is shared between b4420qds.dts and b4860qds.dts Cheers,