On Fri, 2014-06-06 at 00:04 -0500, Liu Shengzhou-B36685 wrote:

quoted

-----Original Message-----
From: linuxppc-release-bounces@linux.freescale.net [mailto:linuxppc-
release-bounces@linux.freescale.net] On Behalf Of Prabhakar Kushwaha
Sent: Monday, April 21, 2014 7:34 PM
To: linuxppc-dev@lists.ozlabs.org
Cc: Wood Scott-B07421; Jain Priyanka-B32167; Aggrwal Poonam-B10812;
Kushwaha Prabhakar-B32579
Subject: [linuxppc-release] [PATCH][v10] powerpc/mpc85xx:Add initial
device tree support of T104x

The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
processor cores with high-performance data path acceleration architecture
and network peripheral interfaces required for networking &
telecommunications.

+
+	iommu@20000 {
+		compatible = "fsl,pamu-v1.0", "fsl,pamu";
+		reg = <0x20000 0x1000>;
+		ranges = <0 0x20000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		interrupts = <
+			24 2 0 0
+			16 2 1 30>;
+		pamu0: pamu@0 {
+			reg = <0 0x1000>;
+			fsl,primary-cache-geometry = <128 1>;
+			fsl,secondary-cache-geometry = <16 2>;
+		};

[Shengzhou]  T1040 RM says:
Hardware coherent PAMU Look-aside caches to improve performance
* A 32-entry, direct-mapped primary PAACT cache
* A 128-entry, 2-way, set-associative secondary PAACT cache
It appears it should be: 
       fsl,primary-cache-geometry = <32 1>;
       fsl,secondary-cache-geometry = <128 2>;

is there any reason that it was "<128 1>,  <16 2>" ?

The B4 device trees are also suspicous.

-Scott