From: Michael Moese=20

On Mon, Feb 03, 2014 at 10:17:43AM +0000, David Laight wrote:
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quoted

We achieved about twice that using the PEX dma controller.

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quoted

Your 3MB/s for single word transfers is similar to what we saw.
Cycle times that make an ISA bus look fast.

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Indeed, this is a really poor performance. I know we could achieve much
more performance using DMA, we have several products where we simply
don't have DMA available - this requires searching for other paths.

I got the host (ppc) to do a dma, not the card. (This does need a
dma controller that is adequately intergrated with the PCIe logic.)
So it doesn't require any hardware changes.
I did have to design the software to minimise the number of single
memory transfers.

My ioremap_wt() could help in these situations, at least increasing
performance for non-DMA operation to a not-that-bad level.

I needed to do writes as well as reads - so I think I would have
needed to map PCIe space fully cached (rather than write-through).
The speed of back to back writes is better than reads (even if they don't
get combined) because the requests get 'posted' and overlap on the
PCIe bus.

Managing cached accesses does get tricky - you need to make sure that
both sides never have to write to the same cache line.

I don't know if other devices could benefit from this, but surely we
got several IPs that would, but those were not yet upstreamed, we're
still working on this.
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Michael
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