-----Original Message-----
From: Wang Dongsheng-B40534
Sent: Tuesday, October 15, 2013 2:51 PM
To: Wood Scott-B07421
Cc: Bhushan Bharat-R65777; linuxppc-dev@lists.ozlabs.org; Wang Dongsheng-=

B40534

Subject: [PATCH v5 4/4] powerpc/85xx: add sysfs for pw20 state and altive=

c idle

=20
From: Wang Dongsheng <redacted>
=20
Add a sys interface to enable/diable pw20 state or altivec idle, and cont=

rol the

dex

);

=20
 #endif /* CONFIG_PPC64 */
=20
+#ifdef CONFIG_FSL_SOC
+#define MAX_BIT				63
+
+static u64 pw20_wt;
+static u64 altivec_idle_wt;
+
+static unsigned int get_idle_ticks_bit(u64 ns) {
+	u64 cycle;
+
+	if (ns >=3D 10000)
+		cycle =3D div_u64(ns + 500, 1000) * tb_ticks_per_usec;
+	else
+		cycle =3D div_u64(ns * tb_ticks_per_usec, 1000);
+
+	if (!cycle)
+		return 0;
+
+	return ilog2(cycle);
+}
+
+static void do_show_pwrmgtcr0(void *val) {
+	u32 *value =3D val;
+
+	*value =3D mfspr(SPRN_PWRMGTCR0);
+}
+
+static ssize_t show_pw20_state(struct device *dev,
+				struct device_attribute *attr, char *buf) {
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+	value &=3D PWRMGTCR0_PW20_WAIT;
+
+	return sprintf(buf, "%u\n", value ? 1 : 0); }
+
+static void do_store_pw20_state(void *val) {
+	u32 *value =3D val;
+	u32 pw20_state;
+
+	pw20_state =3D mfspr(SPRN_PWRMGTCR0);
+
+	if (*value)
+		pw20_state |=3D PWRMGTCR0_PW20_WAIT;
+	else
+		pw20_state &=3D ~PWRMGTCR0_PW20_WAIT;
+
+	mtspr(SPRN_PWRMGTCR0, pw20_state);
+}
+
+static ssize_t store_pw20_state(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	if (value > 1)
+		return -EINVAL;
+
+	smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
+
+	return count;
+}
+
+static ssize_t show_pw20_wait_time(struct device *dev,
+				struct device_attribute *attr, char *buf) {
+	u32 value;
+	u64 tb_cycle;
+	s64 time;
+
+	unsigned int cpu =3D dev->id;
+
+	if (!pw20_wt) {
+		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+		value =3D (value & PWRMGTCR0_PW20_ENT) >>
+					PWRMGTCR0_PW20_ENT_SHIFT;
+
+		tb_cycle =3D (1 << (MAX_BIT - value)) * 2;

Is value =3D 0 and value =3D 1 legal? These will make tb_cycle =3D 0,

+		time =3D div_u64(tb_cycle * 1000, tb_ticks_per_usec) - 1;

And time =3D -1;

+	} else {
+		time =3D pw20_wt;
+	}
+
+	return sprintf(buf, "%llu\n", time > 0 ? time : 0);
}
+
+static void set_pw20_wait_entry_bit(void *val) {
+	u32 *value =3D val;
+	u32 pw20_idle;
+
+	pw20_idle =3D mfspr(SPRN_PWRMGTCR0);
+
+	/* Set Automatic PW20 Core Idle Count */
+	/* clear count */
+	pw20_idle &=3D ~PWRMGTCR0_PW20_ENT;
+
+	/* set count */
+	pw20_idle |=3D ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
+
+	mtspr(SPRN_PWRMGTCR0, pw20_idle);
+}
+
+static ssize_t store_pw20_wait_time(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	u32 entry_bit;
+	u64 value;
+
+	unsigned int cpu =3D dev->id;
+
+	if (kstrtou64(buf, 0, &value))
+		return -EINVAL;
+
+	if (!value)
+		return -EINVAL;
+
+	entry_bit =3D get_idle_ticks_bit(value);
+	if (entry_bit > MAX_BIT)
+		return -EINVAL;
+
+	pw20_wt =3D value;
+	smp_call_function_single(cpu, set_pw20_wait_entry_bit,
+				&entry_bit, 1);
+
+	return count;
+}
+
+static ssize_t show_altivec_idle(struct device *dev,
+				struct device_attribute *attr, char *buf) {
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+
+	value &=3D PWRMGTCR0_AV_IDLE_PD_EN;
+
+	return sprintf(buf, "%u\n", value ? 1 : 0); }
+
+static void do_store_altivec_idle(void *val) {
+	u32 *value =3D val;
+	u32 altivec_idle;
+
+	altivec_idle =3D mfspr(SPRN_PWRMGTCR0);
+
+	if (*value)
+		altivec_idle |=3D PWRMGTCR0_AV_IDLE_PD_EN;
+	else
+		altivec_idle &=3D ~PWRMGTCR0_AV_IDLE_PD_EN;
+
+	mtspr(SPRN_PWRMGTCR0, altivec_idle);
+}
+
+static ssize_t store_altivec_idle(struct device *dev,
+				struct device_attribute *attr,
+				const char *buf, size_t count)
+{
+	u32 value;
+	unsigned int cpu =3D dev->id;
+
+	if (kstrtou32(buf, 0, &value))
+		return -EINVAL;
+
+	if (value > 1)
+		return -EINVAL;
+
+	smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
+
+	return count;
+}
+
+static ssize_t show_altivec_idle_wait_time(struct device *dev,
+				struct device_attribute *attr, char *buf) {
+	u32 value;
+	u64 tb_cycle;
+	s64 time;
+
+	unsigned int cpu =3D dev->id;
+
+	if (!altivec_idle_wt) {
+		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
+		value =3D (value & PWRMGTCR0_AV_IDLE_CNT) >>
+					PWRMGTCR0_AV_IDLE_CNT_SHIFT;
+
+		tb_cycle =3D (1 << (MAX_BIT - value)) * 2;
+		time =3D div_u64(tb_cycle * 1000, tb_ticks_per_usec) - 1;

Likewise

Thanks
-Bharat